Side-by-side comparison
| Parameter | NMOS | PMOS |
|---|---|---|
| Channel carriers | Electrons (n-type channel) | Holes (p-type channel) |
| Threshold voltage V_th | Positive, typically +0.5 to +2 V | Negative, typically −0.5 to −2 V |
| Turn-ON condition | V_GS > V_th (positive gate relative to source) | V_GS < V_th (negative gate relative to source) |
| Carrier mobility | ~450 cm²/V·s (2× faster) | ~200 cm²/V·s |
| Drive strength (same W/L) | ~2× stronger | Weaker; needs 2× wider channel for same current |
| Switching speed | Faster | Slower |
| Source terminal | Connected to GND (low rail) | Connected to V_DD (high rail) |
| Common application | Pull-down network in CMOS logic, low-side switch | Pull-up network in CMOS logic, high-side switch |
| Example devices | 2N7000, BS170, IRF540N | IRF9540N, BSS84, BS250 |
| Body effect | Increases V_th when source is above bulk | Increases |V_th| when source is below bulk |
Key differences
Electron mobility in silicon is ~450 cm²/V·s versus ~200 cm²/V·s for holes — so NMOS delivers roughly twice the current of PMOS for the same gate width. In a CMOS logic gate, PMOS pull-up networks are made twice as wide to balance propagation delay. NMOS connects source to GND and turns on with a positive V_GS; PMOS connects source to V_DD and turns on with V_GS going negative (gate below source). In a 5 V CMOS inverter (CD4069), NMOS V_th ≈ +1.5 V and PMOS V_th ≈ −1.5 V — both see the same input, but respond in complementary fashion. Body effect is more of a problem in NMOS when the source is lifted above the substrate.
When to use NMOS
Use NMOS when you need a fast low-side switch or pull-down device, especially in high-frequency converters or logic gates. The IRF540N switching at 500 kHz in a synchronous buck converter's low-side position handles 33 A with an R_DS(on) of 44 mΩ, and its higher mobility keeps gate charge requirements low.
When to use PMOS
Use PMOS when the circuit requires a high-side switch where the source must connect to V_DD, such as load switches or the pull-up network in CMOS logic. A BSS84 PMOS controls power to a sensor module in a battery-operated system, turning off the rail completely when the gate is driven HIGH.
Recommendation
For speed and efficiency, choose NMOS — it's faster, drives more current per unit area, and dominates in pull-down and low-side roles. Use PMOS when the topology forces the switch to sit between V_DD and the load — not because it's inherently better, but because the circuit demands it.
Exam tip: GATE questions often ask why PMOS transistors are made wider than NMOS in CMOS gates — the answer is mobility ratio (~2:1 electrons to holes), and you must quote both mobility values.
Interview tip: Placement interviewers expect you to explain the body effect in NMOS — specifically how raising the source above the bulk in a stacked configuration increases V_th and reduces current, a real issue in CMOS logic design.