Side-by-side comparison
| Parameter | SR | JK |
|---|---|---|
| Inputs | S (Set), R (Reset) | JK: J (Set), K (Reset) | D: single D |
| Forbidden/Invalid State | S=1, R=1 is forbidden | JK: none | D: none |
| Toggle Condition | Not directly possible | JK: J=1, K=1 toggles | D: not direct |
| Characteristic Equation | Q_next = S + R'Q (with SR≠1) | JK: Q_next = JQ' + K'Q | D: Q_next = D |
| Race-Around Condition | Possible in level-triggered SR | JK level-triggered: yes | D edge-triggered: no |
| Typical IC | CD4043 (SR NAND latch) | JK: 74HC107 | D: 74HC74 |
| Conversion Complexity | Base element | JK: SR + feedback | D: SR with inverter |
| Use in Counters | Rarely used | JK: ripple counters (74HC90) | D: shift registers |
| Setup/Hold Time (typical 74HC) | ~5 ns | JK: ~7 ns | D: ~3 ns |
| Power (74HC, 5V) | Low — microwatts static | Similar across all three in CMOS |
Key differences
The SR flip-flop has the forbidden state S=R=1, which produces undefined output in NAND implementations — this is why it is never used alone in counters. JK eliminates this by toggling when J=K=1, but level-triggered JK (74HC107) suffers race-around if the clock pulse is wider than propagation delay; edge-triggering fixes this. D flip-flop (74HC74) eliminates both issues: one input, no forbidden state, clocks data cleanly on the rising edge at ~3 ns setup time, making it the default element for registers and pipelines.
When to use SR
Use the SR flip-flop when you need a simple set-reset latch for debouncing a mechanical switch with two NAND gates (4011), where the S=R=1 condition physically cannot occur.
When to use JK
Use the D flip-flop (74HC74) whenever you need to register data on a clock edge — shift registers, pipeline stages, and all synchronous counter designs rely on its single-input, no-forbidden-state behaviour.
Recommendation
For placement tests and university design problems, choose the D flip-flop as your default. It converts cleanly to JK or SR and is the building block of every shift register and synchronous counter question you will face.
Exam tip: In GATE and university exams, the most common question is converting one flip-flop type to another — memorise the JK-to-D conversion (D = JQ' + K'Q simplified) and the D-to-T conversion.
Interview tip: Interviewers at core VLSI and embedded companies expect you to explain race-around in JK flip-flops and immediately state that master-slave or edge-triggering resolves it, citing the 74HC107 as a real example.