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Software Defined Radio

SDR architecture, reconfigurability.

Darshan N
Updated: 19 March 2026
11 min read

Traditional radio hardware is designed for a fixed function: an AM receiver cannot become an FM demodulator without hardware changes. Software Defined Radio (SDR) breaks this constraint by moving as much of the radio signal processing as possible into software running on programmable hardware such as DSPs, FPGAs, or general-purpose CPUs. The physical hardware provides only the basic RF front end, while all demodulation, filtering, decoding, and protocol functions are implemented in software that can be updated or replaced. This makes SDR platforms highly flexible and widely used in research, defense, spectrum monitoring, and wireless protocol development.

SDR Architecture: From Antenna to SoftwareAntennaRF FrontEnd (BPF)Filter + LNADownConverterMixer + LOADC(Digitize)High speedSoftware ProcessingDDC, Demod, DecodeProtocol StackDSP / FPGA / CPU / GPUTraditional Radio (comparison)Fixed RFAnalog IFHW DemodHW DecodeAll fixed in hardware
Figure 1: SDR signal chain from antenna to software processing compared to traditional fixed-function hardware radio architecture

Core Concept of SDR

The fundamental idea in SDR is to digitize the RF signal as early as possible in the receive chain, then perform all further processing (filtering, down-conversion, demodulation, decoding, protocol handling) in software. The ideal SDR would place the ADC directly at the antenna output and handle everything in software. In practice, this requires extremely high-speed ADCs (multi-GHz sampling) and enormous computational power. Current SDR platforms make a pragmatic compromise: the RF hardware handles bandpass filtering, low-noise amplification, and down-conversion to an intermediate frequency (IF) or baseband, then digitization occurs at the baseband signal.

The critical hardware component in any SDR is the Direct Conversion Receiver (DCR) or heterodyne front end. The received RF signal is mixed with a local oscillator (LO) signal to produce an in-phase (I) and quadrature (Q) baseband signal. These I/Q samples are digitized by two ADCs and streamed to the host processor. All subsequent processing — matched filtering, timing recovery, equalization, demodulation, and decoding — runs as software on the host.

I/Q Sampling and Baseband Representation

The I/Q (In-phase/Quadrature) representation is central to SDR. Any bandpass signal s(t) centered at frequency fc can be written as s(t) = I(t)*cos(2*pi*fc*t) - Q(t)*sin(2*pi*fc*t). The baseband complex signal x(t) = I(t) + j*Q(t) fully describes s(t) without carrying the carrier frequency information. This is why SDR receivers output complex I/Q samples at the baseband rate rather than RF samples at the carrier frequency. For a signal of bandwidth B, the minimum sampling rate for I/Q samples is B (Nyquist rate on the complex baseband), not 2*fc + B.

Once digitized as I/Q samples, the host software can implement any digital down-conversion (DDC) by multiplying with a digital complex exponential e^(-j*2*pi*delta_f*n/fs) and low-pass filtering. This allows tuning within the captured bandwidth without changing the hardware LO frequency. A single wideband capture can simultaneously process multiple narrowband channels using different DDC configurations in software.

SDR Hardware Platforms

The USRP (Universal Software Radio Peripheral) by Ettus Research is the most widely used academic and research SDR platform. It provides a wideband transceiver front end with interchangeable daughterboards covering different frequency ranges, connected to an FPGA for basic sample processing, and USB/Ethernet/PCIe interface to a host PC. Software frameworks such as GNU Radio provide open-source signal processing blocks that can be assembled graphically or programmatically to implement complete radio systems.

Lower-cost platforms like the RTL-SDR (based on Realtek RTL2832U DVB-T dongle) have made SDR accessible for educational use. These devices support receive-only operation from approximately 25 MHz to 1.75 GHz with up to 2.4 MHz instantaneous bandwidth. Higher-end platforms like the LimeSDR, HackRF, and Ettus X310 support full-duplex operation at wider bandwidths. FPGAs are frequently used within SDR hardware for computationally intensive preprocessing (DDC, DUC) before forwarding samples to the host CPU for protocol-level processing.

Mathematical Expression

The spurious-free dynamic range (SFDR) and noise figure are key parameters of the SDR front end. The sensitivity of a receiver defines the minimum detectable signal power. It is:

P_min = kTB + NF + SNR_min where all terms are in dBm or dB, kTB is thermal noise power, NF is the receiver noise figure, and SNR_min is the minimum required SNR for detection.

Example
Given:
Temperature T = 290 K (room temperature)
Bandwidth B = 200 kHz (GSM channel)
Noise Figure NF = 8 dB
Required SNR_min = 10 dB for demodulation

Why this formula applies:
Receiver sensitivity determines the weakest signal the SDR can detect

Formula:
P_min = 10*log10(kTB) + NF + SNR_min  [all in dBm]

Substitution:
kTB = 1.38e-23 * 290 * 200e3 = 8.004e-16 W
10*log10(kTB) = 10*log10(8.004e-16) + 30 = -120.97 dBm

Calculation:
P_min = -120.97 + 8 + 10

Final Answer: P_min = -102.97 dBm (minimum detectable signal power)
Exam Tip: Thermal noise floor at room temperature is approximately -174 dBm/Hz. For bandwidth B Hz, noise floor = -174 + 10*log10(B) dBm. Adding noise figure and required SNR gives receiver sensitivity. SDR flexibility does not come without cost: ADC resolution (number of bits) directly limits dynamic range as SFDR ≈ 6N dB where N is ADC bit depth.
SDR Reconfigurability: One Hardware, Multiple Radio StandardsSDR HardwareRF Frontend + ADC/DACFM Radio87.5-108 MHzSW: FM demodGSM/LTE900/1800 MHzSW: OFDM RxADS-B1090 MHzSW: OOK decodeWiFi 802.112.4 / 5 GHzSW: OFDM/QAMSpectrumMonitorSW: FFT scanAll functions above implemented as SOFTWARE modules (GNU Radio / Python / C++)Key SDR Platforms ComparisonRTL-SDRRX only25MHz-1.75GHzHackRFHalf duplex1MHz-6GHzLimeSDRFull duplex100kHz-3.8GHzUSRP N310Full duplex10MHz-6GHz
Figure 2: SDR reconfigurability showing how a single hardware platform supports multiple radio standards by changing software modules

Key Mechanism Points

  • SDR digitizes the signal at baseband after down-conversion, producing complex I/Q samples at rate equal to the signal bandwidth rather than at the carrier frequency.
  • GNU Radio is the dominant open-source framework; it provides a flow graph of signal processing blocks (source, filter, demodulator, sink) that execute on a CPU or GPU.
  • ADC resolution determines dynamic range: an N-bit ADC provides approximately 6N dB of SFDR. A 12-bit ADC gives approximately 72 dB dynamic range.
  • I/Q imbalance (amplitude and phase mismatch between I and Q paths) creates image frequency interference; digital calibration algorithms correct this in software.
  • Software reconfigurability enables the same hardware to be updated via firmware/software to support new standards (e.g., upgrading from 4G to 5G NR waveforms) without hardware replacement.

Quick Revision

  • SDR moves signal processing from fixed hardware to reconfigurable software, enabling multi-standard and upgradeable radio platforms.
  • Architecture: Antenna → RF BPF + LNA → Down-converter (Mixer + LO) → ADC → DSP/FPGA/CPU software.
  • I/Q sampling: baseband complex samples at rate B (signal bandwidth). I/Q = cos and sin components after down-conversion.
  • Receiver sensitivity = kTB (dBm) + NF (dB) + SNR_min (dB). Thermal noise floor = -174 + 10*log10(B) dBm.
  • ADC dynamic range ≈ 6N dB for N-bit ADC. SFDR limits the weakest detectable signal in presence of strong interferer.
  • Exam trap: SDR flexibility is limited by ADC sampling rate and resolution; unlimited software flexibility still cannot exceed hardware bandwidth constraints.
  • GNU Radio, USRP, RTL-SDR, HackRF, LimeSDR are standard platforms; USRP+GNU Radio is the academic research standard.

Software Defined Radio Quiz

Test your understanding of SDR architecture, reconfigurability, and baseband processing.

Question 1 of 3

Q1.In an ideal Software Defined Radio architecture, the analog-to-digital converter (ADC) is placed as close to the antenna as possible. According to the Nyquist criterion, if an SDR must digitize a signal with a bandwidth of 20 MHz centered at 2.4 GHz, what minimum sampling rate is required for direct RF sampling?