Clock Skew and Jitter

A chip running at 3 GHz has a clock period of only 333 ps — a 50 ps timing error is 15% of the budget. Clock skew and jitter are the two enemies that steal that margin.

Core Concept

Clock skew is the spatial difference in clock arrival time between two flip-flops in the same chip. It is deterministic — the same offset appears every cycle. Positive skew (late clock at the receiving FF) relaxes setup time but tightens hold time. Negative skew does the opposite.

Clock jitter is the stochastic, cycle-to-cycle variation in clock period caused by power supply noise, phase-locked loop (PLL) imperfections, and substrate coupling. A 74HC-series clock buffer contributes roughly 50 ps RMS jitter. Jitter reduces the effective clock period available to combinational logic.

Modern FPGAs use dedicated clock routing networks (global clock buffers, H-trees) to limit on-chip skew below 200 ps. PLLs on-chip reduce jitter to under 30 ps RMS. Still, both effects must be subtracted from the timing margin in sign-off analysis.

Boolean Expression

The corrected setup constraint with skew and jitter is: T_clk - t_skew - t_jitter ≥ t_pd_ff + t_pd_combo + t_setup. For hold time: t_pd_ff + t_pd_combo ≥ t_hold + t_skew. Positive skew helps setup but hurts hold.

Given:
  T_clk = 10 ns  (100 MHz)
  t_pd_ff = 4 ns, t_pd_combo = 4 ns, t_setup = 1.5 ns
  t_skew = +0.5 ns (positive: receiving FF is late)
  t_jitter = 0.3 ns (peak-to-peak)

Formula / Rule:
  Setup check: T_clk - t_skew - t_jitter >= t_pd_ff + t_pd_combo + t_setup
  Hold check:  t_pd_ff + t_pd_combo >= t_hold + t_skew

Step by step (Setup):
  LHS = 10 - 0.5 - 0.3 = 9.2 ns
  RHS = 4 + 4 + 1.5   = 9.5 ns
  9.2 >= 9.5? --> FAIL (setup violation!)

Step by step (Hold):
  LHS = 4 + 0 = 4 ns  (combo = 0 for direct path)
  RHS = 1 + 0.5 = 1.5 ns
  4 >= 1.5? --> PASS

Final Answer:
  Setup violated — must reduce combo delay or increase T_clk
  Minimum T_clk = 4 + 4 + 1.5 + 0.5 + 0.3 = 10.3 ns --> f_max = 97 MHz

Exam Tip: Positive skew helps setup time (more margin) but hurts hold time (less margin). Negative skew does the reverse. GATE problems often specify skew sign and ask which constraint is violated. Jitter always hurts both setup and hold because it is a worst-case subtraction from T_clk on setup and an addition to the required hold on the other side.

Key Properties

• Clock skew: deterministic, fixed per run, caused by wire length mismatch or buffer delays
• Clock jitter: stochastic, varies cycle to cycle, caused by PLL noise, power supply variation
• 74HC clock buffer jitter: ~50 ps RMS; FPGA global clock network skew: <200 ps
• Positive skew: receiving FF clock is late — setup margin increases, hold margin decreases
• Hold violation is clock-frequency independent; cannot be cured by slowing the clock
• PLL on-chip reduces jitter to <30 ps RMS in modern FPGAs (Xilinx, Intel)
• H-tree clock routing limits skew by balancing wire lengths to all flip-flops

Quick Revision

• Skew = fixed spatial difference in clock arrival time between two registers
• Jitter = cycle-to-cycle random variation in clock period
• Positive skew relaxes setup, tightens hold
• Jitter subtracts from effective T_clk for timing analysis
• Hold violations cannot be fixed by reducing frequency
• H-tree routing and dedicated clock buffers minimize skew on-chip
• PLL on FPGA reduces jitter to <30 ps RMS
• Exam trap: treating positive skew as always bad — it actually helps setup time