1-to-4 Demultiplexer

Every microcontroller's GPIO expander and memory-mapped I/O bus routes one data line to exactly one of four output lines—that routing circuit is a 1-to-4 demultiplexer (DEMUX). The 74HC139 dual 1-to-4 DEMUX does this in a single 16-pin package at 5 V.

Core Concept

A DEMUX receives one data input and steers it to one of several outputs based on select lines. With two select lines S1 and S0, four output combinations exist: 00, 01, 10, 11. The output selected equals the data input D; all others hold logic 0.

The 74HC139 contains two independent 1-to-4 DEMUXes in one package. It operates from 2 V to 6 V, has a typical propagation delay of 7 ns at 5 V, and drives a fan-out of 10 standard HC loads. An active-low enable pin (EN) disables all outputs when high.

DEMUX circuits appear wherever a bus must be time-shared across multiple peripherals. An address decoder asserts EN for only one DEMUX at a time, so data reaches exactly one chip. This is the foundation of memory-mapped I/O in 8085 and ARM Cortex-M systems.

Boolean Expression

Each output follows the form Yn = D · (select decode for n) · EN_bar. Explicitly: Y0 = D·S1'·S0', Y1 = D·S1'·S0, Y2 = D·S1·S0', Y3 = D·S1·S0. The data line D is ANDed with the minterm of the select lines corresponding to that output index. Only one minterm is true at a time, so only one output tracks D.

Given:
  D = 1, S1 = 1, S0 = 0, EN = 0 (active-low, so enabled)

Formula:
  Y0 = D . S1' . S0'
  Y1 = D . S1' . S0
  Y2 = D . S1  . S0'
  Y3 = D . S1  . S0

Step by step:
  S1' = NOT(1) = 0
  S0' = NOT(0) = 1

  Y0 = 1 . 0 . 1 = 0
  Y1 = 1 . 0 . 0 = 0
  Y2 = 1 . 1 . 1 = 1   <-- active output
  Y3 = 1 . 1 . 0 = 0

Final Answer:
  Y2 = 1 (data D routed to output Y2)
  Y0, Y1, Y3 = 0

Exam Tip: Anna University questions frequently swap DEMUX with decoder. A DEMUX has a data input; a decoder does not—its outputs depend only on select/address lines. Also, the 74HC139 outputs are active-low, so Y = 0 means that output is selected. If a question gives active-low outputs, invert your truth table expectations.

Key Properties

• IC: 74HC139 (dual 1-to-4), also 74LS139 in TTL family
• Supply voltage: 2 V to 6 V (HC CMOS), 4.75–5.25 V (LS TTL)
• Propagation delay: 7 ns typical at VCC = 5 V (74HC139)
• Fan-out: 10 HC loads or 20 LS-TTL loads
• Power dissipation: ~0.08 mW static (CMOS), ~35 mW (LS TTL)
• Enable pin: active-low, disables all outputs when EN = 1
• Outputs: active-low on 74HC139; use inverters if active-high outputs needed

Quick Revision

• DEMUX = 1 input, 2^n outputs, n select lines
• 74HC139 = dual 1-to-4, active-low outputs and enable
• Selected output Y = D; all others = 0
• Boolean: Yn = D · (minterm of select lines for n)
• Used for memory-mapped I/O, bus routing, time-multiplexed data lines
• Two 74HC139 chips can build a 1-to-8 DEMUX with one extra gate
• Exam trap: confusing DEMUX with decoder—decoder has no separate data input line