Flip-Flop Timing Parameters

Flip-flop timing parameters define the maximum clock speed of every synchronous digital system. Violating setup time or hold time in a 74HC74 D flip-flop causes metastability — a state that can paralyze an entire CPU pipeline for nanoseconds or longer.

Core Concept

Three parameters govern flip-flop timing. Setup time (t_su) is the minimum time the data input D must be stable before the active clock edge. Hold time (t_h) is the minimum time D must remain stable after the clock edge. Propagation delay (t_pd) is the time from the clock edge to the stable output Q change.

For the 74HC74 positive-edge-triggered D flip-flop: t_su = 20 ns, t_h = 5 ns, t_pd (clock to Q) = 25 ns typical at 5 V supply. The 74LS74 TTL version has t_su = 20 ns, t_h = 5 ns, t_pd = 25 ns at 5 V with 15 mA supply current. Faster devices like the 74FCT74 achieve t_pd = 4.5 ns.

Violating setup or hold time causes metastability — the flip-flop output enters an indeterminate analog state between 0 and 1. It eventually resolves to a valid logic level, but the resolution time is unbounded. This is why clock domain crossing circuits add synchronizer flip-flops with sufficient time for metastability resolution (mean time between failures criteria).

Boolean Expression

The maximum clock frequency is determined by the critical path: f_max = 1 / (t_pd + t_combinational + t_su). Here t_combinational is the propagation delay of logic between two flip-flops. The hold time constraint is: t_pd_min > t_h — the minimum propagation delay of the driving flip-flop must exceed the hold time of the receiving flip-flop to prevent hold violations. If t_pd_min < t_h, a buffer must be inserted.

Given:
  D flip-flop: t_su = 5 ns, t_h = 2 ns, t_pd = 8 ns (min), t_pd = 12 ns (max)
  Combinational logic between two flip-flops: t_comb = 15 ns
  Clock period T = ?

Formula / Rule:
  f_max = 1 / (t_pd_max + t_comb + t_su)
  Hold check: t_pd_min >= t_h

Step by step (setup analysis):
  Minimum T = t_pd_max + t_comb + t_su
  Minimum T = 12 + 15 + 5 = 32 ns
  f_max = 1 / 32 ns = 31.25 MHz

Hold time check:
  t_pd_min = 8 ns
  t_h = 2 ns
  8 >= 2 → hold constraint satisfied, no buffer needed

Final Answer:
  Maximum clock frequency = 31.25 MHz
  Hold time constraint: satisfied (t_pd_min 8 ns > t_h 2 ns).

Exam Tip: GATE consistently tests both setup and hold time calculations in the same problem. Setup time limits maximum frequency (larger t_su → lower f_max). Hold time limits minimum clock period for short paths. A common trap: using t_pd_max for hold time check — you must use t_pd_min because the fastest data arrival is the worst case for hold. Using max propagation delay for hold gives an optimistic (wrong) answer that misses violations.

Key Properties

• Setup time t_su: D must be stable this long before the active clock edge.
• Hold time t_h: D must remain stable this long after the active clock edge.
• Propagation delay t_pd: time from clock edge to valid Q output.
• 74HC74: t_su=20 ns, t_h=5 ns, t_pd=25 ns at 5 V; f_max approximately 40 MHz.
• 74FCT74: t_pd=4.5 ns; used in high-speed pipelined designs.
• f_max = 1 / (t_pd_max + t_comb + t_su) — must use max propagation delay.
• Hold violation: t_pd_min < t_h; fix by inserting buffer to add delay on data path.

Quick Revision

• Setup time: data stable BEFORE clock edge; violation reduces frequency.
• Hold time: data stable AFTER clock edge; violation causes metastability.
• Propagation delay: clock edge to Q valid; use max for setup, min for hold.
• f_max = 1 / (t_pd_max + t_comb + t_su).
• Hold check: t_pd_min >= t_h (use minimum delay).
• Metastability: output stuck between 0 and 1 after timing violation; resolves eventually.
• 74HC74 specs: t_su=20 ns, t_h=5 ns, t_pd=25 ns, 5 V, 80 µA quiescent.
• Exam trap: using t_pd_max instead of t_pd_min in the hold time check gives a falsely safe result and misses hold violations in short clock paths.