Glitches and Races

Glitches and races are the two failure modes that make high-speed combinational circuits in 74F-series and programmable logic devices unreliable at clock frequencies above 50 MHz. A race condition in a latch-based state machine can lock an embedded controller into the wrong state permanently.

Core Concept

A glitch is a narrow spurious pulse at the output of a combinational circuit caused by unequal propagation delays along different signal paths. The most elementary example is F = A · A': when A changes, the AND gate briefly sees both A = 1 and A' = 1 simultaneously because the inverter's propagation delay (10 ns for a 74LS04) has not yet propagated.

A race condition occurs in sequential circuits when two or more state variables change in response to the same input event, and the outcome depends on which flip-flop or latch changes first. In a critical race, different arrival orders lead to different final states. In a non-critical race, the final state is the same regardless of order, but the intermediate path differs.

The 74F74 D flip-flop has tpd(CK→Q) = 5 ns while the 74LS74 has tpd(CK→Q) = 17 ns. If logic downstream uses both Q outputs simultaneously after one clock edge, there is a 12 ns window where the two outputs are inconsistent. This is a real-world critical race scenario in mixed-family PCB designs.

Boolean Expression

Glitch width can be estimated as: t_glitch ≈ |tpd(path1) − tpd(path2)|. For a glitch on F = A · A' through a 74LS04 inverter (tpd = 10 ns): glitch width ≈ 10 ns. Race condition analysis is done through state transition tables and flow tables. A critical race exists when two total states are reachable from the same unstable state depending on which variable changes first.

Given:
Circuit: F = (A AND B) OR (A' AND C)
A transitions: 0 → 1, with B = 1, C = 1
Inverter 74LS04 tpd = 10 ns
AND gate 74LS08 tpd = 14 ns
OR gate 74LS32 tpd = 14 ns

Glitch Analysis:
Path 1 (A direct): A → AND1(A,B) → OR
  A changes at t=0
  AND1 output at t=14 ns  (A=1,B=1 → 1)
  OR output rises at t=28 ns

Path 2 (A inverted): A → INV → AND2(A',C) → OR
  A' falls at t=10 ns
  AND2 output falls at t=24 ns (A'=0,C=1 → 0)
  OR sees AND2 go low at t=24 ns

Timeline:
t=0:    A: 0→1. Path1 AND=0 (A just changed, B=1)
t=10ns: A'→0. AND2(0,1)=0. Path2 going low.
t=14ns: AND1(1,1)=1. Path1 high.
t=24ns: AND2 output confirmed low.
t=28ns: OR settles at 1.

Glitch window: t=24 to t=28 (AND2 low before AND1 high reaches OR)

Final Answer:
Glitch possible width ≈ 4 ns (difference in path timing)
Cure: ensure the two AND gate paths arrive at OR simultaneously
or use a static-hazard-free SOP implementation.

Exam Tip: Anna University questions on races ask you to classify them as critical or non-critical using a flow table. A critical race has two or more different stable states reachable from one unstable state. Non-critical races reach only one stable state regardless of transition order. Glitch questions usually ask for the glitch width — always subtract the shorter path delay from the longer. Do not confuse glitches (combinational) with races (sequential/asynchronous).

Key Properties

• Glitch width ≈ difference in propagation delay between two competing signal paths
• 74LS04 inverter: tpd = 10 ns — sets the minimum glitch width for A·A' circuits
• Critical race: different signal arrival orders lead to different final stable states
• Non-critical race: same final state regardless of transition order, but path differs
• 74F74 vs 74LS74: 5 ns vs 17 ns tpd — 12 ns inconsistency window in mixed-family designs
• Race elimination: use one-hot state encoding, which ensures only one state bit changes per transition
• Glitch elimination: use registered outputs (synchronous design), redundant gates for hazard-free SOP

Quick Revision

• Glitch: spurious pulse in combinational circuit from unequal path delays
• Race condition: outcome depends on which sequential element changes first
• Critical race: two possible stable states from one unstable state
• Non-critical race: one final state regardless of transition order
• Glitch width ≈ |tpd(path1) − tpd(path2)|
• Fix glitches: hazard-free SOP or registered synchronous outputs
• Fix races: one-hot encoding or state assignment that changes only one bit per transition
• Exam trap: calling a non-critical race a critical race — always check whether the final stable state differs, not just the intermediate states