Magnitude Comparator

ALU flag logic in every processor from the 8085 to ARM Cortex-A compares two binary numbers and sets carry, zero, or overflow flags using circuits built from magnitude comparators. The 74HC85 4-bit magnitude comparator does this comparison in a single 16-pin IC with cascade inputs for wider words.

Core Concept

A magnitude comparator determines the relative size of two binary numbers A and B. It produces three outputs: A>B, A=B, and A<B. Exactly one output is high at any time. The comparison starts at the most significant bit and propagates to less significant bits only when higher bits are equal.

The 74HC85 compares two 4-bit words and provides three cascade inputs (IA>B, IA=B, IA<B) to chain multiple chips for 8-bit, 12-bit, or 16-bit comparisons. Propagation delay: 14 ns at 5 V. Supply: 2 V to 6 V. Fan-out: 10 HC loads. Power: ~0.1 mW static.

Cascading two 74HC85 chips compares 8-bit words. Connect the output A>B, A=B, A<B of the LSB stage to the cascade inputs IA>B, IA=B, IA<B of the MSB stage. The MSB stage overrides the LSB result whenever its own bits differ. Set the LSB stage's cascade inputs to 0, 1, 0 (for an initial A=B condition) before connecting.

Boolean Expression

Define equality bit xi = Ai XNOR Bi for each bit position i. Then A=B when x3·x2·x1·x0 = 1 (all bits equal). A>B when A3·B3' is 1, or when x3 and A2·B2' is 1, or when x3·x2 and A1·B1' is 1, and so on. A<B is simply NOT(A>B) AND NOT(A=B). These SOP expressions are implemented inside the 74HC85.

Given:
  A = 1011 (decimal 11)
  B = 1001 (decimal 9)
  Cascade inputs: IA>B=0, IA=B=1, IA<B=0 (initial equal assumption)

Bit-by-bit from MSB:
  A3=1, B3=1 --> equal, go to next bit
  A2=0, B2=0 --> equal, go to next bit
  A1=1, B1=0 --> A1 > B1  --> A > B decided here

(No need to check A0 once a difference is found)

Boolean check:
  x3 = (A3 XNOR B3) = (1 XNOR 1) = 1
  x2 = (A2 XNOR B2) = (0 XNOR 0) = 1
  A1.B1' = 1.NOT(0) = 1.1 = 1
  A>B term: x3.x2.A1.B1' = 1.1.1 = 1

Final Answer:
  A>B = 1, A=B = 0, A<B = 0
  A (decimal 11) > B (decimal 9) confirmed

Exam Tip: When cascading 74HC85 chips, the cascade inputs of the LEAST significant stage must be initialized to 0,1,0 (A>B=0, A=B=1, A<B=0). Setting them to 0,0,0 will produce wrong results. GATE 2017 EC included a cascade connection question where this initialization step was the deciding factor. Anna University also tests this in circuit-design questions involving multi-byte comparisons.

Key Properties

• IC: 74HC85 (CMOS), 74LS85 (TTL, 23 ns delay, 4.75–5.25 V)
• Compares two 4-bit binary numbers; three outputs: A>B, A=B, A<B
• Cascade inputs allow chaining for 8, 12, or 16-bit comparisons
• Propagation delay: 14 ns (74HC85), 23 ns (74LS85)
• Supply: 2–6 V (HC); fan-out: 10 HC loads
• Equality detection uses XNOR of each bit pair
• LSB cascade inputs must be initialized to 0,1,0 for correct cascaded comparison

Quick Revision

• Comparator checks A>B, A=B, A<B; exactly one output high
• Comparison starts at MSB; lower bits only matter if higher bits are equal
• Equality bit xi = Ai XNOR Bi for each position
• 74HC85: 4-bit, cascade inputs allow wider comparisons
• Cascade: output of LSB stage → cascade input of MSB stage
• LSB stage cascade initialization: IA>B=0, IA=B=1, IA<B=0
• Used in ALU condition flag generation, sorting networks, address range checks
• Exam trap: initializing LSB cascade inputs all to 0 instead of the correct 0,1,0 pattern