SISO Shift Register

A Serial In Serial Out (SISO) shift register is the most fundamental type of shift register in digital electronics. It accepts one bit of data at its serial input on each clock pulse and shifts the stored data one position along the register, eventually producing the bits at the serial output one by one. The primary function of a SISO register is to introduce a controlled time delay between input and output, making it an essential building block in digital communication, synchronization, and data buffering circuits.

Core Concept Explanation

In a SISO shift register, D flip-flops are connected in a chain where the Q output of each flip-flop drives the D input of the next. On each rising edge of the clock, every flip-flop captures the value of its D input, which is the previous stage output. This moves data one position to the right with each clock pulse.

Serial input is applied to the D input of the first flip-flop, and the serial output is taken from the Q output of the last flip-flop. If N bits of data are loaded serially, all N bits appear at the output after exactly N clock cycles. The register effectively delays the data stream by N clock periods. This is why SISO registers are also called delay lines.

The internal states of all flip-flops are not directly accessible by external circuitry in a pure SISO configuration. Only the serial output is observed. This makes SISO useful when only the final delayed result matters, such as in digital communication pipelines where data needs to be held up before further processing.

Mathematical Expression

For an N-stage SISO shift register, the output at clock cycle t is equal to the input at clock cycle (t minus N). Mathematically, if the input sequence is x(t), the output is y(t) = x(t - N). The delay introduced is exactly N clock periods. The time delay in seconds is given by T_delay = N times T_clk = N / fclk, where T_clk is the clock period and fclk is the clock frequency.

Practical Understanding

SISO shift registers are used as delay elements in synchronous digital systems where different logic paths must be aligned in time. If one data path takes fewer pipeline stages than another, a SISO register can be inserted to equalize the latency. This is a standard technique in DSP hardware, communication receivers, and processor datapaths.

They are also used in serial communication interfaces to synchronize data received from external sources, which may arrive at a different rate than the internal system clock. The SISO register buffers the incoming bits and allows them to be processed in sequence without loss.

Given:
N = 4-stage SISO shift register, fclk = 10 MHz
Input sequence: 1 0 1 1 (applied MSB first starting at t=0)

Why this formula applies:
Each flip-flop delays data by one clock period
Total delay = N x T_clk

Formula:
T_delay = N / fclk
y(t) = x(t - N)

Substitution:
N = 4, fclk = 10 MHz
T_clk = 1 / 10 MHz = 100 ns
T_delay = 4 x 100 ns

Calculation:
T_delay = 400 ns
Output appears 4 clock cycles after input
CLK1: FF0=1, CLK2: FF0=0 FF1=1, CLK3: FF0=1 FF1=0 FF2=1
CLK4: Serial out = 1 (MSB), CLK5: out=0, CLK6: out=1, CLK7: out=1

Final Answer with units:
Time delay = 400 ns | Output sequence: 1 0 1 1 starting at t = 400 ns

Exam Tip: For a SISO shift register with N stages, data appears at the output after exactly N clock cycles. The delay in time = N/fclk. GATE often gives clock frequency and asks for delay in nanoseconds — simply compute N x T_clk. Also note that intermediate flip-flop values are NOT accessible in SISO.

Quick Revision

• SISO: data enters serially at D of FF0, exits serially from Q of FF(N-1).
• Delay = N clock cycles = N x T_clk = N / fclk in time units.
• Output equation: y(t) = x(t - N) where N is number of stages.
• Intermediate flip-flop states are not accessible externally in pure SISO.
• Primary application: digital delay line, pipeline synchronization.
• Key trap: SISO does not convert serial to parallel; that is SIPO.
• N flip-flops are required to delay data by N clock periods.