SRAM vs DRAM

Every time your CPU fetches an instruction, it reads from memory measured in nanoseconds. The choice between SRAM and DRAM determines whether that fetch takes 1 ns or 60 ns, shaping the entire system's speed.

Core Concept

SRAM uses a bistable latch built from six transistors — four forming two cross-coupled inverters and two acting as pass gates. Because the latch holds its state as long as power is applied, no refresh is required. The AS6C1008 is a popular 128K×8 SRAM with a 55 ns access time and 3.3 V supply.

DRAM stores each bit as charge on a tiny capacitor gated by one NMOS transistor. The capacitor leaks, so the memory controller must refresh every row roughly every 64 milliseconds. The Micron MT4C4001 is a classic 1M×1 DRAM running at 5 V with a 70 ns RAS access time.

SRAM is ten times faster but occupies ten times more silicon area per bit. Modern systems use SRAM for L1 and L2 caches and DRAM for main memory, exploiting the memory hierarchy to hide the latency gap.

Boolean Expression

The SRAM cell cross-coupled latch obeys Q = NOT(Q') at all times when not being written. A write is forced by driving bit lines BL and BL' to opposite values and asserting word line WL = 1. The DRAM read is destructive: sensing the capacitor voltage collapses the stored charge, so every read must be followed by a write-back.

Given:
  SRAM cell with WL=1 (select), BL=1, BL_bar=0
  Initial state Q=0, Q_bar=1

Formula / Rule:
  Write: force Q = BL when WL=1
  Read: sense differential voltage on BL vs BL_bar

Step by step:
  WL=1 enables both access transistors
  BL=1 drives node Q high through left access transistor
  BL_bar=0 drives node Q_bar low through right access transistor
  Cross-coupled inverters latch new state: Q=1, Q_bar=0
  WL=0 isolates cell; state held by latch indefinitely

Final Answer:
  Q=1 stored. No refresh needed. Data retained until next write or power loss.

Exam Tip: GATE often asks why DRAM needs a refresh but SRAM does not. The answer is the storage element: capacitor charge leaks (DRAM) while a flip-flop latch holds state statically (SRAM). Also note that a DRAM read is destructive — the sense amplifier must rewrite the row after reading. SRAM reads are non-destructive. Do not confuse refresh with rewrite.

Key Properties

• SRAM access time: 1-10 ns; DRAM access time: 50-70 ns (DDR4 CL14 ~ 9.7 ns effective burst)
• SRAM cell size: ~6 transistors, 60-100 F² area; DRAM cell: 1T+1C, 6-8 F² — DRAM packs 10x more bits per mm²
• DRAM refresh period: 64 ms at 85°C; refresh current adds ~15 mW per GB
• SRAM is available in both TTL-compatible (5 V) and CMOS (1.8-3.3 V) versions; fan-out 10 for TTL, >50 for CMOS
• DRAM uses multiplexed row/column address (RAS/CAS) to halve pin count; SRAM uses full parallel address
• Power: SRAM standby ~10 µW/Mbit; DRAM active ~100 mW/GB plus refresh overhead
• Typical ICs: SRAM — AS6C1008 (128Kx8, 55 ns); DRAM — MT4C4001 (1Mx1, 70 ns), DDR4 — MT40A1G8 (8 Gb)

Quick Revision

• SRAM = 6 transistors per bit, bistable latch, no refresh, fast, expensive
• DRAM = 1 transistor + 1 capacitor per bit, refresh every 64 ms, slow, cheap, dense
• DRAM read is destructive; sense amplifier rewrites row after every read
• SRAM used for cache (L1/L2/L3); DRAM used for main memory (DDR4/LPDDR5)
• RAS = Row Address Strobe, CAS = Column Address Strobe — DRAM uses these to multiplex address bus
• Refresh interval doubles leakage current at high temperature — critical for embedded DRAM design
• Exam trap: students say 'SRAM is volatile and DRAM is not' — both are volatile; neither retains data without power