ADC Types

An Analog-to-Digital Converter (ADC) is a fundamental building block in embedded systems that converts a continuous analog voltage into a discrete digital number. The choice of ADC architecture directly determines the achievable sampling speed, resolution, and power consumption of the system. For GATE aspirants and engineering students, understanding the trade-offs between SAR, Flash, and Sigma-Delta ADC architectures is essential for both theoretical questions and practical design decisions.

Flash ADC Architecture

A Flash ADC converts the entire analog input to a digital output in a single clock cycle by using 2^N - 1 comparators in parallel, where N is the desired resolution. Each comparator compares the input voltage against a different reference level generated by a precision resistor ladder. The outputs of all comparators form a thermometer code, which is then passed through a priority encoder to generate the N-bit binary output.

Because all comparisons occur simultaneously, the Flash ADC is the fastest possible ADC architecture and can operate in the GHz sampling rate range. However, the hardware cost grows exponentially with resolution. A 4-bit Flash ADC needs 15 comparators; an 8-bit Flash ADC needs 255 comparators; a 10-bit Flash ADC needs 1023 comparators. This exponential scaling makes Flash ADCs impractical for high resolutions and causes high power consumption.

SAR ADC Architecture

The Successive Approximation Register (SAR) ADC uses a binary search algorithm to find the digital code that best represents the analog input. It uses only one comparator and an internal DAC. At each step, the SAR logic sets a trial bit, the DAC generates a trial voltage, and the comparator decides whether the trial voltage is above or below the input. This process repeats N times for an N-bit result.

The SAR ADC requires exactly N clock cycles to complete one conversion, making it predictable and power-efficient. It achieves moderate resolutions (10 to 16 bits) at sampling rates up to tens of megasamples per second. This makes SAR ADCs the default choice in microcontrollers and general-purpose data acquisition systems.

Sigma-Delta ADC Architecture

The Sigma-Delta (or Delta-Sigma) ADC uses a fundamentally different approach: it oversamples the input at a very high rate using a 1-bit comparator and then applies a digital decimation filter to compute a high-resolution result. The modulator shapes quantization noise to push it into high-frequency regions outside the signal band, a process called noise shaping. The decimation filter then averages down the oversampled 1-bit stream, trading speed for resolution.

The oversampling ratio (OSR) is defined as the ratio of the sampling frequency to twice the signal bandwidth (Nyquist rate). Every time the OSR doubles, a first-order Sigma-Delta modulator gains 1.5 bits of resolution (approximately 9 dB SNR improvement). Higher-order modulators gain more bits per doubling. This makes Sigma-Delta the preferred choice for audio digitization and precision measurement instruments requiring 20 to 24 bits of resolution.

Mathematical Expression: SAR Conversion Time

The total conversion time for a SAR ADC is the product of the number of bits N and the clock period T_clk. An additional clock cycle may be needed for sampling and possibly one for output latency, but the dominant term is N cycles. The effective sampling rate is the reciprocal of total conversion time.

Given:
SAR ADC resolution N = 12 bits
Clock frequency f_clk = 20 MHz
Additional overhead = 1 clock cycle (for sampling)
Total cycles per conversion = N + 1 = 13 cycles

Why this formula applies:
SAR ADC performs exactly N comparisons sequentially, each taking one clock cycle.

Formula:
Conversion time T_conv = (N + overhead) / f_clk
Max sampling rate f_s = 1 / T_conv

Substitution:
T_conv = 13 / 20,000,000 = 650 ns
f_s = 1 / 650 ns

Calculation:
f_s = 1 / 0.00000065

Final Answer: Maximum sampling rate = 1.538 MSPS (Mega Samples Per Second)

Exam Tip: For Flash ADC, the number of comparators = 2^N - 1. For SAR ADC, conversion time = N clock cycles. For Sigma-Delta, doubling the OSR gives approximately 1.5 extra bits of resolution per modulator order. These three facts cover the majority of GATE-level ADC architecture questions.

• Flash ADC: 2^N - 1 comparators, single clock cycle conversion, highest speed, lowest resolution, highest power. Used in oscilloscopes.
• SAR ADC: Single comparator with internal DAC, N clock cycles per conversion, medium speed and resolution, low power. Used in microcontrollers.
• Sigma-Delta ADC: 1-bit oversampling modulator with digital decimation filter, very slow, very high resolution (up to 24 bits), excellent for audio and precision DC measurement.
• Noise shaping in Sigma-Delta ADC pushes quantization noise to high frequencies where the decimation filter removes it.
• The fundamental trade-off in ADC design is speed vs. resolution, often summarized by the Walden FOM (Figure of Merit) linking ENOB, bandwidth, and power.

Quick Revision

• Flash ADC comparators = 2^N - 1. For 8-bit: 255 comparators. Conversion in 1 clock cycle.
• SAR ADC conversion time = N clock cycles. 12-bit at 20 MHz clock gives approximately 1.5 MSPS.
• Sigma-Delta doubles OSR for approximately 1.5 extra bits/order of modulator per doubling.
• SAR is the most common ADC in embedded MCUs (STM32, MSP430, PIC).
• Flash ADC used in RF, radar, and oscilloscopes where GHz sampling is needed.
• Sigma-Delta used in audio codecs and precision weighing scales (24-bit resolution).
• Common trap: Sigma-Delta ADC has high latency (many cycles) and is not suitable for rapidly changing signals at high bandwidth.