Output Compare

Generating precise timing signals, delays, or digital waveforms without wasting CPU cycles is a fundamental requirement in embedded systems. Output compare is a timer feature that allows hardware to automatically toggle, set, or clear a GPIO pin when the timer counter reaches a programmed match value, enabling precise signal generation entirely in hardware.

Core Concept: Output Compare Mechanism

In output compare mode, the timer continuously compares the CNT register value against the CCRx register (Capture/Compare Register). When CNT equals CCRx, a match event occurs. The hardware automatically performs a programmed action on the output pin without any CPU intervention. The CCxIF flag is also set, which can trigger an interrupt if enabled.

The action on pin match is controlled by the OCxM bits in the CCMR register. The available modes are: Frozen (no action, interrupt only), Set Active (pin goes high), Set Inactive (pin goes low), Toggle (pin flips state), Force Active, Force Inactive, PWM Mode 1, and PWM Mode 2. Most applications use Toggle for simple square wave generation or PWM modes for duty cycle control.

The output pin must be enabled by setting the CCxE bit in the CCER register. The GPIO pin must also be configured in alternate function mode corresponding to the timer channel. Without the alternate function mapping, the timer output will not appear on the physical pin.

Mathematical Expression: Toggle and Delay Generation

To generate a square wave using the toggle mode, the CCRx value is updated by adding half the desired period in timer ticks after each match event. If the timer clock is F_timer and the desired output frequency is F_out:

Toggle interval in ticks = F_timer / (2 x F_out). Each time the output toggles (half period), CCRx is updated by adding this interval. For a non-blocking precise delay using the frozen mode, the delay in ticks = F_timer x T_delay. CCRx = CNT + delay_ticks at the start. The match interrupt fires after the delay without any polling.

Practical Understanding

Output compare is particularly useful for generating multiple independent non-blocking delays on different channels of the same timer. Since each channel has its own CCRx and independently triggers a match interrupt, four channels can run four independent timing events using one timer. This is far more efficient than using four separate timers.

In PWM mode, CCRx controls the duty cycle. In PWM Mode 1 with up-counting, the output is active (high) while CNT < CCRx and inactive (low) while CNT >= CCRx. The period is fixed by ARR. Duty cycle = (CCRx / (ARR+1)) x 100 percent. Changing CCRx dynamically adjusts duty cycle without stopping the timer.

Given:
Timer clock F_timer = 1 MHz
Desired square wave output frequency = 2 kHz
Output compare mode = Toggle

Why this formula applies:
Toggle mode flips output at each match. Two toggles = one full cycle.

Formula:
Toggle_interval = F_timer / (2 x F_out)

Substitution:
Toggle_interval = 1,000,000 / (2 x 2000)
Toggle_interval = 1,000,000 / 4000

Calculation:
Toggle_interval = 250 ticks

In ISR: CCRx = CCRx + 250 (update for next match)

Final Answer:
Add 250 ticks to CCRx on each match interrupt to generate 2 kHz square wave

Exam Tip: In PWM Mode 1 (up-counting), duty cycle = CCRx / (ARR+1). Setting CCRx = 0 gives 0% duty and CCRx = ARR+1 gives 100% duty. Setting CCRx > ARR produces always-on output. This boundary behavior is a common MCQ trap.

Output Compare Waveforms and PWM Duty Cycle

• OCxM bits in CCMR1/CCMR2 select the output mode: toggle, set, reset, frozen, or PWM.
• CCxE bit in CCER must be set to connect the output compare to the physical GPIO pin.
• In toggle mode, CCRx must be updated in software each ISR call by adding the half-period value.
• PWM duty cycle = CCRx / (ARR+1). Duty can be changed dynamically without stopping the timer.
• Multiple channels on the same timer share CNT and ARR but have independent CCRx and output mode.

Quick Revision

• Output compare fires a hardware action when CNT matches CCRx; no CPU needed for pin toggle.
• Toggle mode: add half-period ticks to CCRx in each ISR to generate square waves.
• PWM Mode 1: output HIGH while CNT less than CCRx, LOW while CNT greater than or equal to CCRx.
• Duty cycle formula: Duty (%) = (CCRx / (ARR+1)) x 100.
• CCxE in CCER enables pin output. OCxM in CCMR selects the compare mode.
• CCRx greater than ARR produces always-on output in PWM Mode 1 (100% duty edge case).
• Four channels per timer allow four independent output events sharing one CNT and ARR.