Timer Basics

Timers are among the most essential peripherals in any microcontroller. They allow precise measurement of time intervals, generation of periodic events, and production of output waveforms without burdening the CPU. Understanding timer basics is fundamental to every embedded application from simple delays to complex motor control.

Core Concept: Timer Architecture

A hardware timer in STM32 consists of three primary registers working together. The Prescaler (PSC) divides the input clock frequency before it reaches the counter. The Counter (CNT) increments or decrements on each clock tick after prescaling. The Auto-Reload Register (ARR) holds the overflow value at which the counter resets and generates an update event.

This three-stage architecture gives flexible control over timing resolution and period. By adjusting PSC, the timer can count slowly for long periods or quickly for high-resolution measurement. By adjusting ARR, the exact overflow period is controlled independently of the prescaler.

STM32 supports three counting modes. In up-counting mode, CNT counts from 0 to ARR then resets. In down-counting mode, CNT counts from ARR to 0 then reloads ARR. In center-aligned mode (also called up/down mode), CNT counts up to ARR then down to 0, used primarily in complementary PWM generation.

Mathematical Expression

The timer output frequency and period are calculated using the following relationships. The timer clock frequency after prescaling is given by dividing the input clock by (PSC+1). The timer overflow frequency is then further divided by (ARR+1). The +1 accounts for the zero-inclusive counting behavior of both registers.

Timer_Clock = APB_Clock / (PSC + 1). This gives the frequency at which CNT increments. The overflow period is: T_overflow = (ARR + 1) / Timer_Clock. The update event interrupt fires at this rate, making it the fundamental repetition period of the timer.

Practical Understanding

Choosing PSC and ARR values involves a trade-off. A large PSC reduces resolution since each CNT step represents a longer time. A large ARR allows longer periods but requires more bits in the counter register. For STM32F4 general-purpose timers, CNT is 16 bits, giving ARR a maximum of 65535. TIM2 and TIM5 have 32-bit counters allowing much longer periods.

The update event generated at overflow can trigger a DMA transfer, an interrupt, or an output signal. This is the foundation of periodic task scheduling without polling. Most RTOS implementations rely on a dedicated timer for system tick generation.

Given:
System APB1 clock = 84 MHz
Desired timer overflow period = 1 ms (1 kHz interrupt rate)

Why this formula applies:
We need to find PSC and ARR values so that (PSC+1)(ARR+1) / Clock = Period

Formula:
(PSC+1) x (ARR+1) = APB_Clock x T_overflow

Substitution:
(PSC+1) x (ARR+1) = 84,000,000 x 0.001 = 84,000

Calculation:
Choose PSC = 83 -> Timer_Clock = 84,000,000 / 84 = 1,000,000 Hz (1 MHz)
Then ARR = (84,000 / 84) - 1 = 1000 - 1 = 999

Final Answer:
PSC = 83, ARR = 999 -> Timer overflows every 1 ms at 84 MHz

Exam Tip: Both PSC and ARR are zero-indexed. The actual divisor is (PSC+1) and (ARR+1). A common mistake is forgetting the +1, which gives a slightly off frequency. Always account for +1 in both registers.

Counter Behavior Visualized

• Up-counting is the default and most commonly used mode in STM32 timers.
• Counter resets to 0 on overflow in up-counting; reloads ARR value in down-counting.
• Center-aligned mode counts up then down, generating symmetric PWM useful in motor drives.
• Update interrupt flag (UIF) in SR register is set on each overflow and must be cleared in ISR.
• TIM1 and TIM8 are advanced timers with complementary outputs; TIM2-TIM5 are general-purpose.

Quick Revision

• Timer_Clock = APB_Clock / (PSC+1); Overflow frequency = Timer_Clock / (ARR+1).
• Three counting modes: up (0 to ARR), down (ARR to 0), center-aligned (up then down).
• ARR is 16-bit for most timers (max 65535); TIM2 and TIM5 have 32-bit counters.
• Update event on overflow triggers interrupt, DMA, or output compare action.
• PSC and ARR are both zero-indexed: actual division = (PSC+1), actual count range = (ARR+1).
• Always clear UIF flag in the update interrupt handler to prevent infinite re-triggering.
• Center-aligned mode fires compare match twice per period: once on way up, once on way down.