Microcontroller Clock and Timing
Instruction Cycle Time
t_{instr} = N_{cycles} \times T_{clk} = \frac{N_{cycles}}{f_{clk}}
| Symbol | Description | Unit |
|---|---|---|
| t_{instr} | Instruction execution time | s |
| N_{cycles} | Clock cycles per instruction | |
| f_{clk} | CPU clock frequency | Hz |
Worked example
ARM Cortex-M0 at 48 MHz. A multiply instruction takes 1 cycle. Find execution time.
Given: f_clk=48 MHz, N_cycles=1
- T_clk = 1/48×10^6 = 20.83 ns
- t_instr = 1 × 20.83 ns = 20.83 ns
Answer: t_instr = 20.83 ns
Timer Count for Desired Delay
N_{count} = \frac{t_{delay}}{T_{clk} \times \text{Prescaler}}
| Symbol | Description | Unit |
|---|---|---|
| N_{count} | Timer count value to load | |
| t_{delay} | Desired time delay | s |
| T_{clk} | CPU/peripheral clock period | s |
| \text{Prescaler} | Timer prescaler divider value |
Worked example
AVR at 8 MHz, Timer0 prescaler=64. Generate 10 ms delay using 8-bit timer. Find count.
Given: f_clk=8 MHz, prescaler=64, t_delay=10×10^−3 s
- Timer tick = 64/8×10^6 = 8 µs per tick
- N_count = 10×10^−3 / 8×10^−6 = 1250
- 8-bit timer max = 255; reload count = 256−1250/5 = need 16-bit or split into 5 overflows
- Per overflow count = 1250/5 = 250, so load 256−250 = 6 into timer
Answer: Load 6 in timer, use 5 overflows for 10 ms
PWM Frequency
f_{PWM} = \frac{f_{clk}}{\text{Prescaler} \times \text{TOP}}
| Symbol | Description | Unit |
|---|---|---|
| f_{PWM} | PWM output frequency | Hz |
| \text{TOP} | Timer compare-match value (period count) | |
| \text{Prescaler} | Timer clock divider |
Worked example
STM32 at 72 MHz, prescaler=72, TOP=1000. Find PWM frequency.
Given: f_clk=72×10^6, prescaler=72, TOP=1000
- f_PWM = 72×10^6 / (72 × 1000) = 72×10^6 / 72000 = 1000 Hz = 1 kHz
Answer: f_PWM = 1 kHz
PWM Duty Cycle
D = \frac{\text{Compare Register Value}}{\text{TOP}} \times 100\%
| Symbol | Description | Unit |
|---|---|---|
| D | Duty cycle | % |
| \text{Compare Value} | OCR (output compare register) value | |
| \text{TOP} | Period count |
Worked example
8-bit PWM timer: TOP=255, OCR=191. Find duty cycle.
Given: OCR=191, TOP=255
- D = 191/255 × 100 = 74.9%
Answer: D ≈ 75%
ADC and DAC Conversion
ADC Resolution (LSB Size)
\Delta V = \frac{V_{ref}}{2^n}
| Symbol | Description | Unit |
|---|---|---|
| \Delta V | Voltage per LSB (resolution) | V |
| V_{ref} | ADC reference voltage | V |
| n | ADC bit resolution | bits |
Worked example
12-bit ADC with Vref=3.3 V. Find resolution in mV.
Given: n=12, Vref=3.3 V
- ΔV = 3.3 / 2^12 = 3.3 / 4096 = 0.000806 V = 0.806 mV
Answer: Resolution = 0.806 mV/LSB
ADC Output Code
D = \frac{V_{in}}{\Delta V} = \frac{V_{in} \cdot 2^n}{V_{ref}}
| Symbol | Description | Unit |
|---|---|---|
| D | Digital output code (integer) | |
| V_{in} | Analogue input voltage | V |
Worked example
12-bit ADC, Vref=3.3 V, Vin=1.65 V. Find digital output code.
Given: n=12, Vref=3.3 V, Vin=1.65 V
- D = 1.65 × 4096 / 3.3 = 6758.4 / 3.3 = 2048
Answer: D = 2048 (half of full-scale, as expected)
ADC Sampling Rate (Nyquist)
f_s \geq 2 f_{max}
| Symbol | Description | Unit |
|---|---|---|
| f_s | Sampling frequency | Hz |
| f_{max} | Maximum signal frequency | Hz |
Worked example
Sensor signal bandwidth = 5 kHz. What minimum sampling rate avoids aliasing?
Given: f_max=5000 Hz
- f_s ≥ 2 × 5000 = 10000 Hz = 10 kHz
- In practice, use f_s = 20–50 kHz for margin
Answer: f_s_min = 10 kHz
DAC Output Voltage
V_{out} = \frac{D}{2^n} \times V_{ref}
| Symbol | Description | Unit |
|---|---|---|
| V_{out} | Analogue output voltage | V |
| D | Digital input code | |
| n | DAC bit resolution | bits |
Worked example
10-bit DAC, Vref=5 V, input code = 512. Find output voltage.
Given: n=10, Vref=5 V, D=512
- Vout = (512/1024) × 5 = 0.5 × 5 = 2.5 V
Answer: Vout = 2.5 V
UART Serial Communication
Baud Rate Register Value (UART)
UBRR = \frac{f_{clk}}{16 \times \text{Baud}} - 1
| Symbol | Description | Unit |
|---|---|---|
| UBRR | UART baud rate register value | |
| f_{clk} | System clock frequency | Hz |
| \text{Baud} | Desired baud rate | bps |
Worked example
AVR at 11.0592 MHz. Set UART to 9600 baud. Find UBRR.
Given: f_clk=11059200 Hz, Baud=9600
- UBRR = 11059200/(16×9600) − 1
- = 11059200/153600 − 1
- = 72 − 1 = 71
Answer: UBRR = 71
Baud Rate Error
\text{Error} = \left(\frac{\text{Actual Baud} - \text{Desired Baud}}{\text{Desired Baud}}\right) \times 100\%
| Symbol | Description | Unit |
|---|---|---|
| \text{Actual Baud} | Baud rate achieved with integer UBRR | bps |
| \text{Desired Baud} | Target baud rate | bps |
Worked example
AT 8 MHz with UBRR=51 for 9600 baud. Find actual baud rate and error.
Given: f_clk=8×10^6, UBRR=51, desired=9600
- Actual = f_clk / (16×(UBRR+1)) = 8×10^6/(16×52) = 8000000/832 = 9615.4 bps
- Error = (9615.4−9600)/9600 × 100 = 15.4/9600 × 100 = 0.16%
Answer: Actual = 9615.4 bps, Error = 0.16%
Bit Transmission Time
t_{bit} = \frac{1}{\text{Baud Rate}}
| Symbol | Description | Unit |
|---|---|---|
| t_{bit} | Time for one bit | s |
| \text{Baud Rate} | Serial communication rate | bps |
Worked example
UART at 115200 baud, 8N1 frame (10 bits total). Find time for one byte.
Given: Baud=115200, bits per byte frame=10
- t_bit = 1/115200 = 8.68 µs
- t_byte = 10 × 8.68 µs = 86.8 µs
Answer: t_byte = 86.8 µs
SPI and I2C Protocols
SPI Transfer Time
t_{transfer} = \frac{N_{bits}}{f_{SCK}}
| Symbol | Description | Unit |
|---|---|---|
| t_{transfer} | Time to transfer N bits | s |
| N_{bits} | Number of bits in transfer | |
| f_{SCK} | SPI clock frequency | Hz |
Worked example
SPI at 4 MHz, transfer 3 bytes (24 bits). Find transfer time.
Given: f_SCK=4×10^6 Hz, N_bits=24
- t = 24 / 4×10^6 = 6×10^−6 s = 6 µs
Answer: t_transfer = 6 µs
I2C Maximum Data Rate
f_{max} = \frac{f_{SCL}}{9} \quad (\text{effective, 8 data + 1 ACK bit per byte})
| Symbol | Description | Unit |
|---|---|---|
| f_{max} | Effective data throughput | bytes/s |
| f_{SCL} | I2C clock frequency | Hz |
Worked example
I2C at standard 100 kHz. Find maximum data throughput in bytes/s.
Given: f_SCL=100000 Hz, bits per byte = 9 (8 data + 1 ACK)
- Throughput = 100000/9 = 11111 bytes/s ≈ 11.1 kB/s
Answer: ≈ 11.1 kB/s
Real-Time Scheduling
CPU Utilisation (Rate Monotonic)
U = \sum_{i=1}^{n} \frac{C_i}{T_i} \leq n(2^{1/n} - 1)
| Symbol | Description | Unit |
|---|---|---|
| U | Total CPU utilisation | |
| C_i | Worst-case execution time of task i | s |
| T_i | Period of task i | s |
Worked example
Three tasks: T1=(C=2ms, T=10ms), T2=(C=3ms, T=15ms), T3=(C=1ms, T=20ms). Check RM schedulability.
Given: U1=2/10=0.2, U2=3/15=0.2, U3=1/20=0.05
- U_total = 0.2+0.2+0.05 = 0.45
- RM bound for n=3: 3×(2^(1/3)−1) = 3×(1.2599−1) = 3×0.2599 = 0.7797
- U_total = 0.45 ≤ 0.78 → schedulable under RM
Answer: Schedulable; U = 0.45 ≤ 0.78
Deadline Miss Condition
\sum_{i=1}^{n} \frac{C_i}{T_i} > 1 \Rightarrow \text{overloaded system}
| Symbol | Description | Unit |
|---|---|---|
| U > 1 | System is guaranteed to miss deadlines |
Worked example
Tasks: T1=(C=8ms, T=10ms), T2=(C=5ms, T=15ms). Will the system be overloaded?
Given: U1=8/10=0.8, U2=5/15=0.333
- U = 0.8 + 0.333 = 1.133
- U > 1 → system is overloaded; deadlines will be missed
Answer: System overloaded; reduce C or increase T
Power Consumption and Battery Life
Dynamic Power Dissipation (CMOS)
P_{dyn} = \alpha C_L V_{DD}^2 f
| Symbol | Description | Unit |
|---|---|---|
| P_{dyn} | Dynamic switching power | W |
| \alpha | Activity factor (0 to 1) | |
| C_L | Load capacitance | F |
| V_{DD} | Supply voltage | V |
| f | Clock frequency | Hz |
Worked example
CMOS logic: α=0.5, CL=10 pF, VDD=3.3 V, f=50 MHz. Find dynamic power.
Given: α=0.5, CL=10×10^−12, VDD=3.3, f=50×10^6
- P_dyn = 0.5 × 10×10^−12 × (3.3)² × 50×10^6
- = 0.5 × 10^−11 × 10.89 × 5×10^7
- = 0.5 × 10^−11 × 5.445×10^8
- = 0.5 × 5.445×10^−3 = 2.72 mW
Answer: P_dyn = 2.72 mW
Battery Life
t_{life} = \frac{C_{battery}}{I_{avg}}
| Symbol | Description | Unit |
|---|---|---|
| t_{life} | Battery life | h |
| C_{battery} | Battery capacity | mAh |
| I_{avg} | Average current consumption | mA |
Worked example
IoT node: 800 mAh battery. Active mode 10 mA for 10% of time, sleep mode 0.01 mA for 90%. Find battery life.
Given: I_active=10 mA, I_sleep=0.01 mA, duty=0.1/0.9
- I_avg = 0.1×10 + 0.9×0.01 = 1 + 0.009 = 1.009 mA
- t_life = 800/1.009 = 793 hours ≈ 33 days
Answer: Battery life ≈ 793 hours (33 days)
Static (Leakage) Power
P_{static} = I_{leak} \times V_{DD}
| Symbol | Description | Unit |
|---|---|---|
| P_{static} | Static power dissipation | W |
| I_{leak} | Leakage current | A |
| V_{DD} | Supply voltage | V |
Worked example
MCU in sleep mode: Ileak=1 µA, VDD=3.3 V. Find static power.
Given: Ileak=1×10^−6 A, VDD=3.3 V
- P_static = 1×10^−6 × 3.3 = 3.3×10^−6 W = 3.3 µW
Answer: P_static = 3.3 µW
Quick reference
| Formula | Expression |
|---|---|
| Instruction Cycle Time | t_{instr} = N_{cycles}/f_{clk} |
| Timer Count for Delay | N = t_{delay}/(T_{clk} \times \text{prescaler}) |
| PWM Frequency | f_{PWM} = f_{clk}/(\text{prescaler}\times\text{TOP}) |
| PWM Duty Cycle | D = OCR/TOP \times 100\% |
| ADC Resolution | \Delta V = V_{ref}/2^n |
| ADC Output Code | D = V_{in} \cdot 2^n/V_{ref} |
| Nyquist Rate | f_s \geq 2f_{max} |
| DAC Output Voltage | V_{out} = (D/2^n)\times V_{ref} |
| UART UBRR | UBRR = f_{clk}/(16\times Baud) - 1 |
| Bit Time | t_{bit} = 1/Baud |
| SPI Transfer Time | t = N_{bits}/f_{SCK} |
| RM Utilisation Bound | U \leq n(2^{1/n}-1) |
| Dynamic Power (CMOS) | P = \alpha C_L V_{DD}^2 f |
| Battery Life | t = C_{battery}/I_{avg} |
| Static Power | P_{static} = I_{leak} V_{DD} |
Exam tips
- GATE ECE embedded questions on ADC frequently ask for digital output code — use D = Vin × 2^n / Vref and always floor (integer truncation), not round.
- UART baud rate error questions require computing the actual baud from the integer UBRR — examiners use 8 MHz intentionally because it gives non-zero error at 9600 baud to test this skill.
- Rate Monotonic schedulability questions in university papers often omit the RM bound formula expecting students to recall n(2^(1/n)−1); for large n this approaches ln(2)=0.693.
- PWM duty cycle for servo motor control (1–2 ms pulse in a 20 ms period) is a frequent lab viva and online exam question — know that OCR = (duty/100) × TOP.
- Battery life calculations for IoT nodes require computing weighted average current across active and sleep states; forgetting to weight by time fraction gives answers 10× too optimistic.
- I2C vs SPI comparison questions are common in ECE technical interviews — highlight that I2C uses 9 bits per byte (including ACK) while SPI is full-duplex with no ACK overhead.