Clock Timing and Execution Time
Clock Period
T = \frac{1}{f_{clk}}
| Symbol | Description | Unit |
|---|---|---|
| T | Clock period | s |
| f_{clk} | Clock frequency | Hz |
Worked example
An 8085 runs at 3 MHz. Find the clock period and the execution time of a 7-T-state instruction.
Given: f_clk = 3 MHz, T-states = 7
- T = 1 / 3×10^6 = 0.333 µs
- Execution time = 7 × 0.333 µs = 2.333 µs
Answer: Clock period = 0.333 µs; execution time = 2.333 µs
Instruction Execution Time (8085)
t_{exec} = N_T \times T
| Symbol | Description | Unit |
|---|---|---|
| t_{exec} | Instruction execution time | s |
| N_T | Number of T-states for the instruction | |
| T | Clock period | s |
Worked example
MOV A, B takes 4 T-states on an 8085 at 5 MHz. Calculate execution time.
Given: N_T = 4, f_clk = 5 MHz
- T = 1 / 5×10^6 = 0.2 µs
- t_exec = 4 × 0.2 µs = 0.8 µs
Answer: 0.8 µs
8086 Bus Cycle Time
t_{bus} = N_{clk} \times T_{clk}
| Symbol | Description | Unit |
|---|---|---|
| t_{bus} | Bus cycle duration | s |
| N_{clk} | Clock cycles in a bus cycle (minimum 4 for 8086) | |
| T_{clk} | Clock period | s |
Worked example
An 8086 at 8 MHz performs a minimum bus cycle. Calculate bus cycle time.
Given: N_clk = 4, f_clk = 8 MHz
- T_clk = 1 / 8×10^6 = 125 ns
- t_bus = 4 × 125 ns = 500 ns
Answer: 500 ns
Wait States Required
N_w = \lceil \frac{t_{acc} - t_{avail}}{T_{clk}} \rceil
| Symbol | Description | Unit |
|---|---|---|
| N_w | Number of wait states needed | |
| t_{acc} | Memory access time | s |
| t_{avail} | Time available without wait states | s |
| T_{clk} | Clock period | s |
Worked example
8086 at 10 MHz interfaces with EPROM having 450 ns access time. Available time = 300 ns. Find wait states.
Given: t_acc = 450 ns, t_avail = 300 ns, T_clk = 100 ns
- Deficit = 450 − 300 = 150 ns
- N_w = ceil(150 / 100) = ceil(1.5) = 2
Answer: 2 wait states required
Memory Addressing and Chip Select
Number of Address Lines Required
N_{addr} = \log_2(\text{Memory Size in Bytes})
| Symbol | Description | Unit |
|---|---|---|
| N_{addr} | Number of address lines needed | |
| \text{Memory Size} | Total addressable memory | Bytes |
Worked example
How many address lines are needed to address 64 KB of memory?
Given: Memory size = 64 KB = 65536 bytes
- N_addr = log2(65536)
- N_addr = log2(2^16) = 16
Answer: 16 address lines
Memory Map Range
\text{End Address} = \text{Start Address} + \text{Size} - 1
| Symbol | Description | Unit |
|---|---|---|
| \text{Start Address} | Beginning of memory block | hex |
| \text{Size} | Size of memory chip | Bytes |
| \text{End Address} | Last address in block | hex |
Worked example
A 4 KB ROM is mapped starting at 8000H in 8085. Find its end address.
Given: Start = 8000H, Size = 4 KB = 1000H bytes
- End = 8000H + 1000H − 1
- End = 9000H − 1 = 8FFFH
Answer: 8000H to 8FFFH
Number of Memory Chips Required
N_{chips} = \frac{\text{Total Memory Required}}{\text{Capacity per Chip}}
| Symbol | Description | Unit |
|---|---|---|
| N_{chips} | Number of chips | |
| \text{Total Memory} | System memory needed | Bytes |
| \text{Capacity per Chip} | Single chip capacity | Bytes |
Worked example
Design a 32 KB RAM system using 8K×8 RAM chips.
Given: Total = 32 KB, Chip capacity = 8 KB
- N_chips = 32 KB / 8 KB = 4 chips
Answer: 4 chips required
8086 Segment + Offset to Physical Address
\text{PA} = (\text{Segment} \times 16) + \text{Offset}
| Symbol | Description | Unit |
|---|---|---|
| \text{PA} | Physical address (20-bit) | hex |
| \text{Segment} | Segment register value (16-bit) | hex |
| \text{Offset} | Effective address within segment | hex |
Worked example
CS = 1200H, IP = 0500H. Find physical address of next instruction.
Given: CS = 1200H, IP = 0500H
- PA = 1200H × 10H + 0500H
- PA = 12000H + 0500H = 12500H
Answer: Physical Address = 12500H
Interrupt Timing (8085)
Interrupt Latency (8085)
t_{lat} = t_{recognition} + t_{CALL}
| Symbol | Description | Unit |
|---|---|---|
| t_{lat} | Interrupt latency | T-states |
| t_{recognition} | Interrupt recognition delay (3–5 T-states) | T-states |
| t_{CALL} | CALL instruction T-states (18 T-states) | T-states |
Worked example
8085 at 3 MHz. Interrupt recognized after 3 T-states, CALL takes 18 T-states. Find latency in µs.
Given: f = 3 MHz, t_recognition = 3 T, t_CALL = 18 T
- T = 1/3 MHz = 0.333 µs
- Total T-states = 3 + 18 = 21
- t_lat = 21 × 0.333 = 7 µs
Answer: 7 µs
TRAP Vector Address
\text{TRAP ISR address} = 0024H
| Symbol | Description | Unit |
|---|---|---|
| 0024H | Fixed jump address for TRAP interrupt | hex |
Worked example
Where does control transfer when 8085 TRAP interrupt fires?
Given: TRAP is non-maskable; vector address is fixed
- TRAP always vectors to 0024H regardless of interrupt mask
- PC ← 0024H after saving return address on stack
Answer: 0024H
RST n Vector Address
\text{Vector} = n \times 8
| Symbol | Description | Unit |
|---|---|---|
| n | RST number (0–7) | |
| \text{Vector} | ISR start address | hex |
Worked example
Find the vector address for RST 5 in 8085.
Given: n = 5
- Vector = 5 × 8 = 40 (decimal)
- 40 decimal = 28H
Answer: 0028H
Stack and Subroutine Operations
Stack Pointer After PUSH
SP_{new} = SP_{old} - 2
| Symbol | Description | Unit |
|---|---|---|
| SP_{new} | Stack pointer after push | hex |
| SP_{old} | Stack pointer before push | hex |
Worked example
SP = 2100H. After executing PUSH B, find SP.
Given: SP_old = 2100H
- SP_new = 2100H − 2 = 20FEH
- B stored at 20FFH, C stored at 20FEH
Answer: SP = 20FEH
Stack Pointer After POP
SP_{new} = SP_{old} + 2
| Symbol | Description | Unit |
|---|---|---|
| SP_{new} | Stack pointer after pop | hex |
| SP_{old} | Stack pointer before pop | hex |
Worked example
SP = 20FEH. After POP H, find SP.
Given: SP_old = 20FEH
- SP_new = 20FEH + 2 = 2100H
- L ← [20FEH], H ← [20FFH]
Answer: SP = 2100H
Return Address on Stack After CALL
\text{Return Address} = PC_{CALL} + 3
| Symbol | Description | Unit |
|---|---|---|
| PC_{CALL} | Address of CALL instruction | hex |
| 3 | Bytes occupied by CALL instruction | bytes |
Worked example
CALL instruction is at 2050H. What return address is pushed?
Given: PC_CALL = 2050H, CALL = 3 bytes
- Return address = 2050H + 3 = 2053H
- 2053H is pushed onto stack
Answer: 2053H
8255 PPI and I/O Port Interfacing
8255 Control Word — Mode 0
CW = 1 \cdot D_7 + \text{Port config bits}
| Symbol | Description | Unit |
|---|---|---|
| D_7 | Must be 1 for mode set command | |
| \text{Port config bits} | D6–D0 define port modes and directions |
Worked example
Configure 8255 in Mode 0: Port A = output, Port B = input, Port C = output.
Given: D7=1, D6D5=00 (Mode 0 A), D4=0 (A out), D3=0 (CU out), D2=0 (Mode 0 B), D1=1 (B in), D0=0 (CL out)
- D7=1, D6=0, D5=0, D4=0, D3=0, D2=0, D1=1, D0=0
- CW = 1000 0010 = 82H
Answer: Control Word = 82H
I/O Port Address Calculation
\text{Port Address} = \text{Base Address} + \text{Offset}
| Symbol | Description | Unit |
|---|---|---|
| \text{Base Address} | Chip-select defined starting address | hex |
| \text{Offset} | A1A0 bits: 00=PA, 01=PB, 10=PC, 11=CW |
Worked example
8255 base address = 80H. Find address of control register.
Given: Base = 80H, CW offset = 03H
- CW address = 80H + 03H = 83H
Answer: Control register at 83H
8253/8254 Timer Calculations
Timer Output Frequency
f_{out} = \frac{f_{clk}}{N}
| Symbol | Description | Unit |
|---|---|---|
| f_{out} | Output frequency | Hz |
| f_{clk} | Input clock frequency | Hz |
| N | Count value loaded in register |
Worked example
8253 timer clocked at 2 MHz, count = 200. Find output frequency.
Given: f_clk = 2 MHz, N = 200
- f_out = 2×10^6 / 200 = 10,000 Hz = 10 kHz
Answer: 10 kHz
Count Value for Desired Frequency
N = \frac{f_{clk}}{f_{desired}}
| Symbol | Description | Unit |
|---|---|---|
| N | Count value to load | |
| f_{clk} | Timer input clock | Hz |
| f_{desired} | Required output frequency | Hz |
Worked example
Generate 1 kHz using 8253 with 1 MHz clock. Find count value.
Given: f_clk = 1 MHz, f_desired = 1 kHz
- N = 1×10^6 / 1×10^3 = 1000
- Load 1000 (03E8H) into count register
Answer: N = 1000 (03E8H)
Timer Delay (Mode 0)
t_{delay} = N \times T_{clk}
| Symbol | Description | Unit |
|---|---|---|
| t_{delay} | Delay duration | s |
| N | Count loaded | |
| T_{clk} | Timer clock period | s |
Worked example
8253 in Mode 0 with 2 MHz clock, N = 5000. Find delay.
Given: N = 5000, f_clk = 2 MHz
- T_clk = 1/2×10^6 = 0.5 µs
- t_delay = 5000 × 0.5 µs = 2500 µs = 2.5 ms
Answer: 2.5 ms
Data Transfer Rate and DMA
Data Transfer Rate
DTR = f_{clk} \times \text{bits per transfer}
| Symbol | Description | Unit |
|---|---|---|
| DTR | Data transfer rate | bps |
| f_{clk} | Transfer clock frequency | Hz |
| \text{bits per transfer} | Word size | bits |
Worked example
8086 transfers 16-bit words at 8 MHz bus clock. What is maximum DTR?
Given: f_clk = 8 MHz, bits = 16
- DTR = 8×10^6 × 16 = 128×10^6 bps = 128 Mbps
Answer: 128 Mbps
DMA Transfer Time
t_{DMA} = \frac{N_{bytes}}{DTR}
| Symbol | Description | Unit |
|---|---|---|
| t_{DMA} | Total DMA transfer time | s |
| N_{bytes} | Number of bytes to transfer | bytes |
| DTR | DMA transfer rate | bytes/s |
Worked example
DMA transfers 4 KB block at 1 MB/s. Find transfer time.
Given: N_bytes = 4096, DTR = 1×10^6 bytes/s
- t_DMA = 4096 / 1×10^6 = 4.096 ms
Answer: 4.096 ms
Quick reference
| Formula | Expression |
|---|---|
| Clock Period | T = 1/f_{clk} |
| Instruction Execution Time | t_{exec} = N_T \times T |
| Wait States | N_w = \lceil (t_{acc} - t_{avail}) / T_{clk} \rceil |
| Address Lines | N_{addr} = \log_2(\text{Size}) |
| Memory End Address | \text{End} = \text{Start} + \text{Size} - 1 |
| 8086 Physical Address | PA = CS \times 16 + IP |
| RST Vector | \text{Vector} = n \times 8 |
| TRAP Vector | 0024H (fixed) |
| PUSH Effect on SP | SP_{new} = SP - 2 |
| POP Effect on SP | SP_{new} = SP + 2 |
| CALL Return Address | RA = PC_{CALL} + 3 |
| Timer Output Frequency | f_{out} = f_{clk}/N |
| Count for Frequency | N = f_{clk}/f_{desired} |
| Timer Delay | t_{delay} = N \times T_{clk} |
| DMA Transfer Time | t_{DMA} = N_{bytes}/DTR |
Exam tips
- GATE examiners frequently ask the physical address calculation for 8086 — always multiply segment by 16 (shift left one hex digit), not 8.
- For 8085 timing questions, identify T-state count from the instruction set table; MOV takes 4, MVI takes 7, LDA/STA take 13.
- 8255 control word questions require D7 = 1 for mode set; forgetting this makes the byte a port C bit-set command instead.
- Memory interfacing numericals always ask how many address lines are decoded by the chip-select logic — count only the lines NOT used by the chip itself.
- 8253 mode questions test Mode 0 (interrupt on terminal count) vs Mode 2 (rate generator) — output waveform shape distinguishes them in BARC and ISRO papers.
- Stack pointer always decrements by 2 on PUSH (16-bit pair) and increments by 2 on POP; confusing this with byte operations is a common error in university papers.