Interview questions & answers
Q1. Explain the operating principle of an N-channel enhancement MOSFET.
An N-channel enhancement MOSFET has no conducting channel at zero gate voltage; when VGS exceeds the threshold voltage Vt (~1–3 V for discrete MOSFETs), an inversion layer of electrons forms under the oxide between drain and source, creating a conductive channel. The 2N7000 NMOS with Vt = 2.1 V begins conducting when VGS > 2.1 V, and ID increases quadratically with (VGS - Vt) in the saturation region. Unlike a BJT, the gate draws essentially zero DC current because the gate oxide (SiO2) is an insulator, making MOSFET bias circuits far simpler and more power-efficient.
Follow-up: Why does drain current saturate when VDS > VGS - Vt?
Q2. What is threshold voltage (Vt) and what factors affect it?
Threshold voltage is the minimum VGS required to form a strong inversion layer (conducting channel) under the gate oxide, and it depends on oxide thickness, gate material work function, substrate doping, and oxide charge. The IRF540 power NMOS has Vt = 2–4 V; thinner gate oxide (as in modern 7 nm CMOS) reduces Vt to ~0.3 V to allow operation at 0.7 V supply. Vt decreases with increasing temperature (~-2 to -4 mV/°C for silicon) and can be modulated by substrate (body) bias, which is exploited in DRAM and SRAM cells for leakage control.
Follow-up: What is the body effect and how does it shift the threshold voltage?
Q3. What are the three operating regions of a MOSFET and their conditions?
The cutoff region (VGS < Vt) has no channel and essentially zero drain current; the linear (triode) region (VDS < VGS - Vt) has the channel fully formed with ID proportional to VDS, acting as a voltage-controlled resistor; the saturation region (VDS ≥ VGS - Vt) has a pinched-off channel at the drain end and ID is controlled only by VGS via ID = (k/2)(VGS - Vt)². The IRF540 operating as an analog switch uses the triode region (Ron ≈ 44 mΩ at VGS = 10 V), while the same device used as an amplifier biases in saturation.
Follow-up: What is channel length modulation and how does it affect the saturation region?
Q4. Compare MOSFET and BJT in terms of switching and analog applications.
MOSFETs have higher input impedance (gate oxide, essentially infinite DC impedance vs BJT's rπ ≈ kΩ), faster switching at high voltages due to no minority carrier storage, and lower drive power, making them dominant in digital logic and power switching. BJTs provide higher transconductance (gm = IC/VT ≈ 40 mA/V at 1 mA vs MOSFET's 1–5 mA/V at same current), making them preferred in low-noise RF amplifiers and precision analog circuits. In audio amplifier output stages, power MOSFETs like the IRF640 are preferred over TIP35 BJTs because they have positive temperature coefficient of Ron, preventing thermal runaway.
Follow-up: Why do MOSFETs not suffer from thermal runaway like BJTs?
Q5. What is the MOSFET's on-resistance (RDS_on) and why is it critical in power applications?
RDS_on is the drain-to-source resistance when the MOSFET is fully enhanced (in the deep triode region), and it directly determines conduction losses: Pcond = ID² × RDS_on. The IRF540 has RDS_on = 44 mΩ at VGS = 10 V, so at 10 A drain current the conduction loss is 4.4 W. Modern power MOSFETs like the CSD18540Q5B have RDS_on = 5 mΩ, reducing the same loss to 0.5 W — a 9× improvement that translates directly to higher efficiency in synchronous buck converters running at 99%+ efficiency.
Follow-up: Why does RDS_on increase with temperature in a power MOSFET?
Q6. Explain CMOS inverter operation and its significance.
A CMOS inverter consists of a PMOS transistor (source to VDD) and NMOS transistor (source to GND) with their gates tied together and drains tied to the output; when Vin = 0 (low), PMOS is on and NMOS is off, so Vout = VDD, and when Vin = VDD, NMOS is on and PMOS is off, Vout = 0. In a 65 nm CMOS process with VDD = 1.0 V, both transistors are never simultaneously fully on in static states, so steady-state current is only leakage (nA range), giving near-zero static power dissipation. This is why CMOS (not NMOS or TTL) became the universal choice for digital ICs — the static power advantage enabled integration of billions of transistors.
Follow-up: When does a CMOS inverter dissipate significant power?
Q7. What is the gate charge (Qg) of a power MOSFET and why does it matter for switching loss?
Gate charge is the total charge that must be supplied to (or removed from) the gate to fully turn on or off the MOSFET, and it determines the switching energy loss per cycle: Esw = Qg × VGS × fsw. The IRF540 has Qg = 71 nC; at 100 kHz switching and VGS = 12 V, gate drive loss = 71 nC × 12 V × 100 kHz = 85 mW. High-frequency designs use MOSFETs with lower Qg (e.g., Si7336ADP with Qg = 10 nC) to reduce driver power and improve efficiency in DC-DC converter applications.
Follow-up: What is the Miller plateau on the gate charge curve and what does it represent?
Q8. What is subthreshold conduction in a MOSFET and why does it matter in digital design?
Subthreshold conduction is the small exponential drain current that flows even when VGS < Vt, following ID ∝ exp(VGS/nVT), with a 60 mV/decade swing at room temperature as the fundamental lower limit for MOSFET switching. In a 28 nm CMOS process with billions of transistors, even 1 nA subthreshold leakage per transistor × 10^9 transistors = 1 A total leakage current at idle, which is the dominant power challenge in modern mobile SoCs. Threshold voltage optimization — high-Vt cells for leakage-critical paths and low-Vt cells for speed-critical paths — is a key technique in low-power IC design.
Follow-up: What is the subthreshold slope and why is 60 mV/decade a physical limit?
Q9. What is the body effect in a MOSFET and in what circuit does it cause problems?
The body effect is the increase in threshold voltage when the source-to-body voltage (VSB) is non-zero, caused by widening of the depletion layer under the channel: Vt = Vt0 + γ(√(2φF + VSB) - √(2φF)). In a multi-stage source-follower chain, each stage has VSB > 0 because the source is above ground, shifting Vt upward and reducing gate drive headroom. In CMOS analog design, bulk-driven MOSFET circuits avoid the body effect by connecting all NMOS substrates to the most negative supply, which is why body connections must be explicitly considered in layout.
Follow-up: How is the body effect exploited as a second transconductance (gmb) in some analog CMOS circuits?
Q10. How does a power MOSFET differ from a small-signal MOSFET in structure?
Power MOSFETs use a vertical DMOS structure where thousands of parallel hexagonal or stripe cells share a common drain contact on the bottom of the chip, allowing extremely low RDS_on and high current handling that would be impossible with a planar lateral structure. The IRF540 has a die area of ~40 mm² with ~50,000 parallel cells, giving 110 A rated current, while a BC546 equivalent planar small-signal MOSFET handles only ~100 mA. The vertical structure also allows high breakdown voltages (several hundred volts) without requiring proportionally long channel lengths.
Follow-up: What is the parasitic body diode in a power MOSFET and how does it affect synchronous rectifier operation?
Q11. What is the Miller effect in MOSFETs and how does it affect amplifier design?
The Miller effect in a MOSFET amplifier multiplies the gate-drain capacitance Cgd by (1 + |Av|) at the input node, creating a large effective input capacitance that limits bandwidth. A CS amplifier built with a 2N7002 (Cgd = 1.5 pF) with Av = -20 creates an effective Miller capacitance of 31.5 pF at the input; with 1 kΩ source resistance, this gives f-3dB = 1/(2π × 1kΩ × 31.5pF) ≈ 5 MHz. The cascode topology eliminates this by keeping the CS transistor's drain nearly at AC ground, limiting Av of that stage to ~1 and extending bandwidth into the GHz range.
Follow-up: Why is Cgd (gate-drain capacitance) more problematic than Cgs for amplifier bandwidth?
Q12. Explain the concept of the MOSFET as an analog switch.
In the triode region, a MOSFET's channel behaves as a resistor with value Ron = 1/(µnCox(W/L)(VGS - Vt - VDS/2)), controlled by VGS, making it an electronically variable resistor or analog switch. The CD4066 bilateral switch uses CMOS transmission gates (NMOS + PMOS in parallel) to pass analog signals with Ron ≈ 200 Ω at 5 V, allowing audio signal routing in mixing consoles. The key non-ideality is that Ron varies with VDS (signal amplitude), causing harmonic distortion in audio applications unless the switch is used with small signal swings relative to VGS overdrive.
Follow-up: What is the charge injection error in a MOSFET sample-and-hold circuit?
Q13. What is channel length modulation in MOSFETs and how is it modeled?
Channel length modulation is the increase in ID with VDS in the saturation region, caused by the pinch-off point moving toward the source as VDS increases, effectively shortening the channel. It is modeled by ID = (k/2)(VGS - Vt)²(1 + λVDS), where λ (channel length modulation parameter) ≈ 0.01–0.1 V^-1 for typical processes — the output resistance ro = 1/(λID) = |VA|/ID where VA is the Early voltage analog for MOSFETs. For a BSIM3 model of a 180 nm NMOS at ID = 1 mA with VA = 20 V, ro = 20 kΩ, which limits achievable gain in single-stage CMOS amplifiers.
Follow-up: How does increasing channel length affect channel length modulation?
Q14. What is the significance of the oxide capacitance (Cox) in MOSFET design?
Cox = εox/tox (oxide capacitance per unit area) determines the amount of inversion charge induced per volt of gate bias, directly setting the transconductance (gm = µnCox(W/L)(VGS - Vt)) and hence the speed and gain achievable for a given transistor size. At 7 nm technology, tox is equivalent to ~1 nm SiO2 thickness (using high-k HfO2), giving Cox ≈ 35 fF/µm² versus 3.5 fF/µm² for 130 nm technology — a 10× increase that allows 10× higher drive current at the same gate voltage. However, thin oxides also mean higher leakage current through the gate, which is why high-k dielectrics replaced SiO2 below 45 nm.
Follow-up: What is high-k gate dielectric and why did the semiconductor industry adopt it?
Q15. How do you calculate the drain current of an NMOS in saturation?
In saturation (VDS ≥ VGS - Vt), drain current is ID = (µnCox/2)(W/L)(VGS - Vt)², where µnCox is the process transconductance parameter (kn', typically 100–300 µA/V² for older processes), W/L is the width-to-length ratio set by layout. For a 180 nm NMOS with kn' = 270 µA/V², W/L = 10, VGS = 1.8 V, Vt = 0.5 V: ID = (270µ/2)(10)(1.3)² = 2.28 mA. This square-law relationship means that doubling (VGS - Vt) quadruples ID, unlike the exponential BJT relation — a trade-off that makes MOSFET analog design less efficient in gain per milliamp but more linear over voltage.
Follow-up: Why is the MOSFET's square-law I-V relationship advantageous for mixer design?
Common misconceptions
Misconception: MOSFET gate draws no current at all, even at high frequencies.
Correct: At DC, gate current is essentially zero because of the oxide insulator, but at high frequencies the gate capacitance (Cgs, Cgd) draws significant charging current that the gate driver must supply.
Misconception: Threshold voltage is a fixed constant for a given MOSFET type.
Correct: Threshold voltage varies with temperature (-2 to -4 mV/°C), body bias (body effect), and device-to-device process variation, and can shift under hot carrier stress over the device lifetime.
Misconception: A MOSFET in the saturation region is always fully on and conducting maximum current.
Correct: Saturation in a MOSFET means the channel is pinched off at the drain end and current is controlled by VGS; maximum current flows only in the deep triode (linear) region at maximum VGS and minimum VDS.
Misconception: CMOS logic dissipates no power because complementary transistors never conduct simultaneously.
Correct: CMOS dissipates dynamic power during switching proportional to C×VDD²×f, subthreshold leakage power, and short-circuit current during input transitions when both PMOS and NMOS are partially on.