How it works
For enhancement MOSFETs, three biasing methods are common. Gate bias uses a voltage divider R1 and R2 to fix VGS directly: since IG = 0, no current flows through the divider into the gate, so VGS = VDD × R2/(R1+R2) exactly. This is stable against load changes but not against VTN variation between devices. Self-bias (drain-feedback bias) connects the gate directly to the drain: VGS = VDS, forcing the device into saturation automatically and providing negative feedback. Voltage divider with source resistor RS adds stability: VGS = VG − ID × RS, and if ID rises, VGS falls, reducing ID — the same feedback principle as BJT emitter degeneration. The Q-point is found by solving ID = (kn/2)(VGS − VTN)² simultaneously with the load line VDS = VDD − ID(RD + RS).
Key points to remember
Because gate current IG = 0, gate bias resistors can be in the megohm range (1 MΩ–10 MΩ) without loading the signal source — a major advantage over BJT biasing. Self-bias ensures VGS = VDS ≥ VGS − VTN only if VTN > 0, so it automatically guarantees saturation for enhancement MOSFETs. Q-point graphical solution requires drawing the bias line VGS = VG − ID × RS on the transfer characteristic curve ID vs VGS. Transconductance gm = 2ID/(VGS − VTN) at the Q-point must be calculated to find voltage gain AV = −gm × RD. Unlike BJTs, MOSFETs have no thermal runaway issue from VBE temperature dependence, but VTN still shifts with temperature (about −2 mV/°C).
Exam tip
The examiner always asks you to find the Q-point of a MOSFET voltage divider bias circuit — calculate VGS from the divider (remember IG = 0), then substitute into ID = (kn/2)(VGS − VTN)² and verify VDS = VDD − ID × RD.