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Key formulas
| Name | Formula | Variables / Notes |
|---|---|---|
| Memory Address Range | Addresses = 2^N | N = number of address lines; 8085 has 16 address lines, giving 2^16 = 65536 locations (64 KB) |
| Instruction Cycle Time | T_instruction = N_states x T_clock | N_states = number of T-states for the instruction; T_clock = 1 / f_clock; e.g., MOV r1,r2 takes 4 T-states at 3 MHz = 1.33 us |
| Stack Pointer Operation | SP = SP - 1 (PUSH), SP = SP + 1 (POP) | SP = 16-bit Stack Pointer register; stack grows downward in memory; PUSH decrements SP before storing; POP increments SP after reading |
| Interrupt Priority | TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR | TRAP is non-maskable; RST 7.5/6.5/5.5 are maskable via SIM instruction; INTR is lowest priority general interrupt |
Key concepts
Register Architecture
The 8085 has one 8-bit accumulator (A), six general-purpose 8-bit registers (B, C, D, E, H, L) usable as three 16-bit pairs (BC, DE, HL), a 16-bit program counter (PC), a 16-bit stack pointer (SP), and a flags register with five flags: S, Z, AC, P, CY.
Addressing Modes
Immediate: operand in instruction (MVI A, 32H). Register: operand in register (MOV A, B). Register Indirect: address in register pair (MOV A, M uses HL). Direct: 16-bit address in instruction (LDA 2050H). Implicit: operand implied (CMA complements A).
Instruction Groups
Data Transfer: MOV, MVI, LDA, STA, LHLD, SHLD, XCHG. Arithmetic: ADD, SUB, INR, DCR, DAD. Logical: ANA, ORA, XRA, CMA, CMC, RLC, RAL. Branch: JMP, JZ, JNZ, JC, CALL, RET. Machine Control: NOP, HLT, EI, DI, SIM, RIM.
Flag Register
Carry (CY): set when arithmetic produces a carry out of bit 7. Zero (Z): set when result is 00H. Sign (S): set when bit 7 of result is 1 (negative). Parity (P): set when result has even number of 1s. Auxiliary Carry (AC): set on carry from bit 3 to bit 4, used for BCD operations.
Timing and Control Signals
ALE (Address Latch Enable) goes high during T1 to indicate the lower 8 bits of the multiplexed AD0-AD7 bus carry an address. IO/M distinguishes memory (low) from I/O (high) operations. RD and WR are active-low read and write strobes.
Interrupts
TRAP (RST 4.5) vectors to 0024H, non-maskable, edge and level triggered. RST 7.5 vectors to 003CH, maskable, edge triggered, has a latch. RST 6.5 vectors to 0034H, maskable, level triggered. RST 5.5 vectors to 002CH, maskable, level triggered. INTR uses the data bus to supply a restart address.
Tables
8085 Register Summary
| Register | Size | Purpose |
|---|---|---|
| A (Accumulator) | 8-bit | ALU operations, I/O |
| B, C | 8-bit / 16-bit BC | General purpose |
| D, E | 8-bit / 16-bit DE | General purpose |
| H, L | 8-bit / 16-bit HL | Memory pointer (M) |
| PC | 16-bit | Next instruction address |
| SP | 16-bit | Stack top pointer |
| Flags (F) | 5 bits used | S, Z, AC, P, CY |
Instruction T-States and Bytes
| Instruction | Bytes | T-States |
|---|---|---|
| MOV r1, r2 | 1 | 4 |
| MVI r, data | 2 | 7 |
| LDA addr | 3 | 13 |
| STA addr | 3 | 13 |
| ADD r | 1 | 4 |
| JMP addr | 3 | 10 |
| CALL addr | 3 | 17 |
| RET | 1 | 10 |
Interrupt Vector Table
| Interrupt | Vector Address | Type |
|---|---|---|
| TRAP | 0024H | Non-maskable, edge+level |
| RST 7.5 | 003CH | Maskable, edge |
| RST 6.5 | 0034H | Maskable, level |
| RST 5.5 | 002CH | Maskable, level |
| INTR | Supplied on bus | Maskable, level |
Quick facts
- The 8085 operates at a maximum clock frequency of 3 MHz (standard) and 5 MHz (8085A-2 variant).
- AD0-AD7 is a multiplexed address-data bus; ALE separates address from data in T1.
- The 8085 can address 64 KB of memory (16 address lines) and 256 I/O ports (8-bit I/O address).
- CALL instruction takes 17 T-states; this is the highest T-state count among common instructions.
- The DAA (Decimal Adjust Accumulator) instruction corrects the result of BCD addition using AC and CY flags.
- SIM instruction sets the interrupt mask and RST 7.5 flip-flop; RIM reads interrupt masks and serial input.
- XCHG swaps HL with DE in a single 4 T-state instruction, useful for pointer manipulation.
- A NOP instruction takes 4 T-states and is 1 byte; used for timing delays or placeholder code.
Exam shortcuts
- To find execution time: multiply T-states by T_clock (T_clock = 1/f). For a 2 MHz clock, T_clock = 0.5 us; MOV (4 T-states) takes 2 us. Always confirm clock frequency in the problem.
- For delay loop calculations: total T-states = (T-states of loop body) x loop_count + overhead. A loop using DCR B and JNZ costs 4 + 7 = 11 T-states per iteration when branch is taken, 4 + 4 = 8 on last pass.
- Identify addressing mode by inspection: if the operand is a number (32H), it is immediate. If it is a register (B, C), it is register. If it is M, it is register indirect via HL. If a 16-bit address appears, it is direct.
- For stack questions, trace SP manually: initial SP = 2099H; PUSH BC decrements SP twice (SP becomes 2097H) and stores B at 2098H, C at 2097H. POP reverses this.
- Carry flag after addition: if sum of unsigned values exceeds FFH, CY = 1. Carry flag after subtraction (SUB): CY = 1 means borrow occurred (result is negative in unsigned sense).