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Key formulas
| Name | Formula | Variables / Notes |
|---|---|---|
| CMOS Inverter Switching Threshold | V_M = (V_tp + V_DD / 2 + (V_tn * sqrt(k_n/k_p))) / (1 + sqrt(k_n/k_p)) | V_M: switching threshold (V); V_tp: PMOS threshold voltage (negative, V); V_tn: NMOS threshold voltage (V); k_n, k_p: process transconductance parameters (A/V²); V_DD: supply voltage (V) |
| Propagation Delay (RC model) | t_p = 0.69 * R * C_L | t_p: propagation delay (s); R: equivalent ON resistance of the transistor (Ω); C_L: load capacitance (F); 0.69 = ln(2) |
| Dynamic Power Dissipation | P_dyn = α * C_L * V_DD² * f | P_dyn: dynamic power (W); α: activity factor (0 to 1, fraction of cycles with switching); C_L: load capacitance (F); V_DD: supply voltage (V); f: clock frequency (Hz) |
| Short-Circuit Power | P_sc = I_mean * V_DD | P_sc: short-circuit power (W); I_mean: average short-circuit current during transition (A); V_DD: supply voltage (V) |
| NMOS Drain Current (Linear Region) | I_D = μ_n C_ox (W/L) [(V_GS - V_tn)V_DS - V_DS²/2] | I_D: drain current (A); μ_n: electron mobility; C_ox: oxide capacitance per unit area (F/cm²); W/L: transistor aspect ratio; V_GS: gate-source voltage (V); V_tn: threshold voltage (V); V_DS: drain-source voltage (V) |
Key concepts
CMOS Complementary Logic
Every CMOS gate has a pull-up network (PUN) of PMOS transistors and a pull-down network (PDN) of NMOS transistors. The PUN is the dual of the PDN. PMOS in series implements AND in the PUN; NMOS in parallel implements OR in the PDN.
Transistor Scaling
In constant field scaling by factor S > 1: dimensions (W, L, t_ox) shrink by S; V_DD shrinks by S; doping increases by S. Power per gate scales as 1/S²; power density stays roughly constant; delay improves by 1/S.
Latch-Up in CMOS
Parasitic NPN and PNP transistors in the CMOS substrate form a SCR (thyristor) structure. If triggered by a voltage spike, the SCR latches ON and causes large current, potentially destroying the device. Prevented by guard rings and proper layout spacing.
Static CMOS Noise Margins
Noise margin high: NM_H = V_OH - V_IH. Noise margin low: NM_L = V_IL - V_OL. For a symmetric CMOS inverter, both noise margins are ideally V_DD/2. Larger noise margins indicate better noise immunity.
Elmore Delay Model
For a transistor chain in a PDN/PUN, the Elmore delay is the sum over each node of (resistance from node to output) times (capacitance at that node). Used to estimate delay through series-connected transistors without full SPICE simulation.
Tables
CMOS Gate Transistor Count and Complexity
| Gate | NMOS Count | PMOS Count |
|---|---|---|
| Inverter | 1 | 1 |
| NAND2 | 2 (series) | 2 (parallel) |
| NOR2 | 2 (parallel) | 2 (series) |
| NAND3 | 3 (series) | 3 (parallel) |
| AOI21 (AND-OR-INV) | 3 | 3 |
CMOS Scaling Rules (Scale Factor S > 1)
| Parameter | Scaling | Effect |
|---|---|---|
| Channel length L | 1/S | Faster switching |
| Supply voltage V_DD | 1/S | Lower power |
| Gate capacitance C_g | 1/S | Lower energy/switch |
| Current I_D | 1/S | Smaller drive |
| Power per gate | 1/S² | Lower dissipation |
| Gate density | S² | More gates per mm² |
Quick facts
- Minimum feature size in leading-edge processes (2024): 3 nm (TSMC, Samsung); 2 nm in production by 2025.
- Dynamic power dominates in high-speed CMOS; static (leakage) power becomes significant below 90 nm.
- Reducing V_DD by 2x reduces dynamic power by 4x, but also reduces speed and noise margin.
- NMOS is roughly 2x to 2.5x faster than PMOS for the same W/L due to higher electron mobility.
- Standard cell height in a 7 nm process is typically 6 to 7.5 metal tracks.
- Activity factor α for a random CMOS logic node is typically 0.1 to 0.3.
- Gate oxide thickness t_ox in modern processes is 1 to 2 nm, requiring high-k dielectrics to limit tunneling leakage.
Exam shortcuts
- To find PDN for a complex gate, write the Boolean expression for when output is pulled LOW (when F = 0). NMOS in series implements AND; NMOS in parallel implements OR. Then form the dual for the PUN (swap series and parallel, use PMOS). This direct method avoids trial and error.
- Propagation delay ratio between two inverters of different sizes: t_p scales linearly with transistor W for fixed C_L (larger W gives smaller R, so smaller delay). If W doubles, delay halves. Use this to size transistors for a target delay without full calculation.
- For dynamic power problems: P = α C V² f. If frequency doubles and V_DD is reduced by sqrt(2), power stays the same. This tradeoff appears in questions about voltage-frequency scaling.