Simulating Digital Counter Waveforms

A digital counter increments or decrements its stored binary value on each clock edge. The output waveforms of a counter have a clear frequency relationship: Q0 toggles at half the clock frequency, Q1 at one quarter, Q2 at one eighth, and so on. Simulating counter waveforms lets you verify this relationship, confirm that reset and enable signals work correctly, and check that a modulo-N counter wraps around at the right count. This tutorial covers a 3-bit ripple counter, a 4-bit synchronous counter, and a modulo-6 counter.

• How to configure a clock source with a specific frequency and duty cycle
• How to place and wire a 3-bit ripple counter in the simulator
• How to read the output waveforms and verify the frequency division relationship
• How to add an asynchronous reset and confirm the counter clears to 000
• How to modify the counter to count only to a specific modulus using preset or NAND logic

• Understanding that a T flip-flop or JK flip-flop in toggle mode divides the clock frequency by 2
• Familiarity with binary counting sequence and carry propagation
• Basic knowledge of asynchronous versus synchronous reset in flip-flops

1. Step 1: Open the Counter lab
   Navigate to the Digital section of ECExplain and select Counter Waveforms. The canvas loads with a 3-bit ripple counter consisting of three JK flip-flops connected in cascade. The CLK input of the first flip-flop is connected to a clock source. The Q output of each flip-flop drives the CLK input of the next. All J and K inputs are tied high.
   Tip: Confirm that J and K are both tied to logic 1 before running. If either is left floating the flip-flop will not toggle and the counter will not advance.
2. Step 2: Configure the clock source
   Click the clock source block at the top left of the canvas. Set the frequency to 1 kHz, duty cycle to 50%, and initial level to 0. This gives a clean 1 kHz square wave. The simulation will run for 10 milliseconds by default, covering 10 complete clock cycles.
   Tip: Keep the frequency low enough that the waveform display shows at least four complete cycles of Q0 without zooming. At 1 kHz with a 10 ms simulation window, you will see 10 clock cycles and 5 cycles of Q0.
3. Step 3: Add probes and run
   Place a probe on CLK, Q0, Q1, and Q2. In the probe manager, name them CLK, Q0, Q1, and Q2 respectively. Click Run. The waveform panel displays four stacked traces. CLK toggles at 1 kHz. Q0 should toggle at 500 Hz, Q1 at 250 Hz, and Q2 at 125 Hz. Verify this by counting transitions in the waveform panel.
   Tip: Use the zoom-to-fit button to center all four waveforms in the panel. If the traces overlap, adjust the trace height using the vertical spacing slider on the left side of the waveform panel.
4. Step 4: Verify the binary count sequence
   Zoom in to display exactly 8 clock cycles. Reading Q2, Q1, Q0 from top to bottom at each rising edge of CLK, the sequence should be: 000, 001, 010, 011, 100, 101, 110, 111, then return to 000. Use the cursor tool to step through each clock edge and confirm the bit pattern at each step matches this sequence.
   Tip: In a ripple counter, Q0 changes immediately at the CLK edge, but Q1 changes slightly after Q0 (when Q0 goes low), and Q2 changes slightly after Q1. This ripple delay appears as small staggered transitions in the waveform. This delay does not exist in synchronous counters.
5. Step 5: Test asynchronous reset
   Click the Reset button in the input control panel to pulse the CLR (clear) input of all three flip-flops simultaneously. The waveform shows Q2, Q1, and Q0 all going to 0 at the moment CLR goes high, regardless of the clock state. After CLR returns low, the counter resumes counting from 000.
   Tip: An asynchronous reset acts immediately, not on the next clock edge. If the reset pulse is shorter than one clock period, the counter will still clear correctly because the CLR input overrides the flip-flop state independently of CLK.
6. Step 6: Build a modulo-6 counter
   Switch the circuit selector to 'Modulo-N Counter'. Set the modulus to 6. The simulator adds a NAND gate with inputs connected to Q1 and Q2. The NAND output connects to the CLR pins of all flip-flops. When the counter reaches 6 (binary 110, so Q2=1 and Q1=1), the NAND output goes low for one brief instant, clearing the counter to 000. Run the simulation. The count sequence should be: 000, 001, 010, 011, 100, 101, then back to 000, skipping 110 and 111.
   Tip: The clear glitch at count 6 produces a very brief spike on Q1 and Q2 waveforms that may be visible if the simulation time step is small enough. This is the state 6 being detected and immediately cleared. In real hardware this glitch is often unavoidable in ripple-based modulo-N counters.
7. Step 7: Switch to synchronous 4-bit counter
   Use the circuit selector to switch to '4-bit Synchronous Counter'. All four flip-flops now share the same CLK line. Add a probe for Q3. Run the simulation. The waveform shows all four outputs changing simultaneously at each clock edge, with no ripple delay between them. Q3 toggles at 62.5 Hz (1 kHz divided by 16). The full count sequence runs from 0000 to 1111 before resetting.
   Tip: Compare the synchronous counter waveform to the ripple counter waveform using overlay mode. The difference in edge alignment between Q0, Q1, Q2 is clearly visible: the ripple counter shows staggered edges while the synchronous counter shows aligned edges.

For the 3-bit ripple counter at 1 kHz: the waveform panel shows four traces. CLK has a period of 1 ms. Q0 has a period of 2 ms. Q1 has a period of 4 ms. Q2 has a period of 8 ms. The binary count sequence from 000 to 111 completes in exactly 8 clock cycles and repeats. For the modulo-6 counter: the count reaches 101 on the fifth clock edge, then resets to 000 on the sixth clock edge. Q2 and Q1 never remain high simultaneously for a full clock period.

• Q0 toggles correctly but Q1 never changes: the connection between Q0 output and the CLK input of the second flip-flop is broken. In a ripple counter this link is essential. Check the wire routing on the canvas and reconnect if it is missing.
• Counter counts up but never resets in modulo-6 mode: the NAND gate inputs are connected to Q0 and Q1 instead of Q1 and Q2. State 6 is binary 110, which means Q2 and Q1 are both high. Reconnecting the NAND inputs to Q2 and Q1 will fix this.
• All outputs jump to 1 at the start and then go to 0: the flip-flops have a preset initial state of 1 because the preset (PRE) pin is accidentally tied low. Set PRE to logic 1 (inactive) for all flip-flops and re-run.
• Synchronous counter shows the same ripple delay as the ripple counter: the CLK inputs of the flip-flops are not all connected to the same source. Verify in the netlist that every CLK pin connects to the single clock source node, not to the Q output of the previous stage.
• Waveform display shows only CLK and one Q output despite four probes being placed: the waveform panel display count is limited in the current view. Scroll down in the waveform panel or increase the panel height to reveal all traces.