Simulating JK Flip Flop Behaviour

The JK flip flop is a clocked bistable circuit with two inputs, J and K, and two complementary outputs, Q and Q'. Unlike the SR flip flop, the JK has no forbidden input state. When both J and K are 1, the output toggles on every clock edge. This tutorial takes you through all four J and K input combinations and confirms the toggle behaviour that makes the JK flip flop useful in counters.

• How the JK flip flop differs from the SR flip flop by eliminating the undefined state
• What happens to Q and Q' for each of the four J,K input combinations
• How to observe the toggle condition J=1, K=1 across multiple clock pulses
• How the current state Q feeds back into the next state in toggle mode

• Understanding of SR flip flop operation and its forbidden state
• Knowledge of clock-edge triggering in flip flops
• Familiarity with complementary outputs Q and Q'

1. Step 1: Check initial state
   Open the JK flip flop simulator. You will see two toggle switches labeled J and K on the left, a CLK button in the center panel, and two LED indicators labeled Q and Q' on the right. Note the initial state of Q before you do anything.
   Tip: The initial state may be Q=0 or Q=1 depending on the simulator. Record it so you can predict what happens for each subsequent clock pulse.
2. Step 2: Test J=0, K=0 (no change)
   Set both J and K to 0. Click CLK once. Observe that Q does not change. Click CLK a second time. Q should still not change. The J=0, K=0 condition holds the current state regardless of how many clock pulses are applied.
   Tip: Apply at least two clock pulses here to confirm that the hold behaviour is consistent, not just a coincidence of the initial state.
3. Step 3: Test J=1, K=0 (set)
   Set J to 1 and K to 0. Click CLK once. Q should go to 1 and Q' should go to 0, regardless of the previous state. Click CLK again. Q should remain at 1 because J=1 K=0 forces the set state.
   Tip: If Q is already 1 before this step, the LED will not visibly change on the first pulse. Click CLK a second time to confirm it stays at 1.
4. Step 4: Test J=0, K=1 (reset)
   Set J to 0 and K to 1. Click CLK once. Q should go to 0 and Q' should go to 1. Click CLK again. Q should remain at 0.
   Tip: This is the complement of the previous step. After this step Q should be 0. Use this as a known starting point before testing the toggle condition.
5. Step 5: Test J=1, K=1 (toggle), first pulse
   Confirm Q is currently 0 from the previous step. Set both J and K to 1. Click CLK once. Q should flip to 1 and Q' should flip to 0.
   Tip: Write down Q before the pulse and predict Q after the pulse. Toggle means the output after is always the complement of the output before.
6. Step 6: Test J=1, K=1 (toggle), second pulse
   With J and K still both at 1, click CLK again. Q should flip back to 0 and Q' should return to 1. Apply a third pulse. Q should go to 1 again.
   Tip: Apply at least four consecutive clock pulses in this mode. Each pulse should reverse Q. If Q is not alternating, check that both J and K are truly set to 1.
7. Step 7: Record the full truth table
   Using your notes from steps 2 through 6, fill in the four rows of the JK flip flop characteristic table: J=0 K=0 (no change), J=0 K=1 (reset to 0), J=1 K=0 (set to 1), J=1 K=1 (toggle). Confirm each row matches your observed output.
   Tip: The no-change row should list Q(t+1) = Q(t), and the toggle row should list Q(t+1) = Q(t)' to reflect state dependence.

Q remains unchanged for J=0 K=0. Q becomes 1 for J=1 K=0. Q becomes 0 for J=0 K=1. For J=1 K=1, Q alternates between 0 and 1 on each clock edge, and Q' is always the complement of Q in every case. At no point should Q and Q' both be 0 or both be 1 simultaneously.

• If Q and Q' are both showing the same state, the simulator has entered an invalid output. Reset the flip flop and restart from step 1.
• If the toggle condition does not alternate and Q stays fixed at 1 with J=1 K=1, check that the K toggle is actually ON. It is common to set J to 1 but leave K at 0, which is the set condition, not the toggle condition.
• If Q changes without a clock pulse, the simulator may be level-triggered rather than edge-triggered. In that case, hold J and K steady and only change them after clicking CLK.
• If Q does not respond to CLK at all, the flip flop may be held in reset by an active low reset or preset line. Look for an additional RST or PRE control on the simulator panel.
• If the toggle appears to happen on every other pulse rather than every pulse, count your clicks carefully. Holding the CLK button briefly may be registering as two edges on some simulators.