How to Simulate a PLL Circuit

A phase-locked loop locks the frequency and phase of a voltage-controlled oscillator to a reference signal. The loop consists of a phase detector, a low-pass loop filter, and a VCO connected in a feedback path. When the loop is out of lock, the VCO frequency drifts toward the reference frequency. Once locked, the phase error settles to a small constant value. This tutorial uses the ECExplain PLL simulator to observe lock acquisition, steady-state phase error, and the effect of loop filter bandwidth on locking speed.

• How to configure the VCO free-run frequency and sensitivity in the simulator
• How to set the reference signal frequency and observe initial phase error
• How to interpret the phase error plot during lock acquisition
• How the loop filter cut-off frequency affects how fast the loop locks
• How to identify lock range and capture range from the simulation output

• Basic understanding of feedback systems and control loops
• Familiarity with frequency, phase, and the concept of a voltage-controlled oscillator
• Knowledge of low-pass filter cut-off frequency and its effect on signal bandwidth

1. Step 1: Open the PLL lab
   Go to the Analog section of ECExplain and select PLL Circuit. The simulator canvas shows four blocks connected in a loop: Phase Detector (PD), Loop Filter (LF), VCO, and a feedback path from VCO output back to PD. A reference frequency source is connected to the other input of the PD.
   Tip: Take a moment to trace the signal flow before changing any values. The PD output is a voltage proportional to the phase difference. The LF smooths this voltage. The VCO output frequency shifts in response to the filtered voltage.
2. Step 2: Set VCO parameters
   Click the VCO block. In the property panel, set the free-run frequency to 1 MHz and the VCO sensitivity (K_v) to 100 kHz per volt. This means a 1 V change at the VCO input will shift the output frequency by 100 kHz. Leave the output amplitude at its default of 1 V peak.
   Tip: The free-run frequency is the VCO output frequency when its input voltage is 0 V. Setting it equal to the reference frequency minimizes the initial frequency error and speeds up lock acquisition in simulation.
3. Step 3: Set the reference signal
   Click the Reference Source block. Set its frequency to 1 MHz and amplitude to 1 V. This matches the VCO free-run frequency, so the loop starts close to lock. Click Run. The phase error plot in the output panel should show a waveform that quickly converges toward 0 or a small constant value.
   Tip: If you want to observe the full lock acquisition process, set the reference to 1.05 MHz (50 kHz above the VCO free-run). The loop will take longer to lock and the phase error will show larger initial oscillations before settling.
4. Step 4: Observe phase error convergence
   In the output panel, select the Phase Error plot from the trace selector. The y-axis shows phase error in radians and the x-axis shows time. During lock acquisition the phase error oscillates with decreasing amplitude. Once the amplitude falls below approximately 0.1 radians and stays there, the loop is in lock. Note the time at which lock is achieved.
   Tip: The lock time depends on the loop filter bandwidth and the loop gain. Narrow loop filter bandwidth generally means slower lock acquisition but better noise rejection once locked.
5. Step 5: Change loop filter bandwidth
   Click the Loop Filter block. Change the cut-off frequency from its default of 10 kHz to 50 kHz. Re-run the simulation. The phase error plot should show faster convergence compared to the previous run. Use the overlay mode to display both runs on the same plot and compare the lock acquisition times directly.
   Tip: Increasing loop bandwidth speeds up lock acquisition but also allows more high-frequency phase noise through the loop. In real PLL design, bandwidth is chosen as a compromise between these two effects.
6. Step 6: Measure the VCO output frequency
   Switch the output panel trace selector to VCO Output Frequency. The plot shows how the instantaneous VCO frequency changes over time. Initially it sits at 1 MHz. If the reference was set to 1.05 MHz, the VCO frequency should increase from 1 MHz toward 1.05 MHz as the loop acquires lock and then stay at 1.05 MHz in steady state.
   Tip: The simulator calculates instantaneous frequency by tracking zero crossings of the VCO output waveform. Short-time variations in this measurement are normal and do not indicate a problem.
7. Step 7: Test the lock range
   Increase the reference frequency in steps of 20 kHz, starting from 1 MHz, and re-run after each change. Record whether the loop achieves lock by checking whether the phase error converges. Continue until the phase error no longer converges. The highest reference frequency at which the loop still locks is the edge of the lock range. With K_v = 100 kHz/V and a supply range of plus or minus 5 V, the theoretical lock range is plus or minus 500 kHz around the free-run frequency.
   Tip: When the loop fails to lock, the phase error plot will show a sawtooth-like waveform that does not converge. This is called cycle slipping. The frequency at which this first appears is the edge of the capture range, which is narrower than the lock range.

With VCO free-run at 1 MHz, reference at 1 MHz, and loop filter cut-off at 10 kHz: the phase error plot shows rapid convergence to near 0 radians within the first 200 microseconds of simulation time. VCO output frequency remains at 1 MHz throughout. With reference at 1.05 MHz and loop filter at 50 kHz: the phase error oscillates for approximately 100 microseconds before settling, and the VCO frequency trace increases from 1 MHz and locks at 1.05 MHz.

• Phase error never converges and the plot shows unbounded growth: the loop gain is too high, causing instability. Reduce K_v to 50 kHz/V or lower the loop filter cut-off frequency to reduce loop bandwidth and restore stability.
• VCO output frequency stays at the free-run value even after several milliseconds: the phase detector output is not reaching the VCO input. Check the netlist to confirm the loop filter output node is connected to the VCO input pin and not left floating.
• Lock is achieved but with a large steady-state phase error: a second-order loop filter is required to reduce steady-state phase error to zero for a frequency step input. The default first-order filter will always have a finite steady-state phase error proportional to the frequency offset.
• Simulation runs slowly or freezes: the time step is too small for the 1 MHz carrier. The simulator needs at least 10 samples per cycle of the highest frequency signal. For 1 MHz this means a time step no larger than 100 ns. If the default step is smaller than this, increase the minimum step size in solver settings.
• Reference frequency source shows no waveform in the output panel: the probe is placed on the wrong node. Verify that the probe is attached to the junction between the reference source and the PD input, not to the VCO output.