Visual
Course overview
This course covers VLSI design from MOS transistor physics through CMOS combinational and sequential logic, layout rules, and timing analysis. It is structured for students encountering VLSI for the first time as well as those reviewing for exams. The course progresses from device-level understanding to gate design, layout verification, and static timing analysis. After completing it, students can design and analyze CMOS circuits, apply design rules, and interpret timing constraints in digital integrated circuit design.
Details
Target audience: Third or fourth-year B.Tech ECE students taking VLSI Design as a core or elective subject, or preparing for GATE.
Duration: 12 to 14 hours
Prerequisites
- Semiconductor physics: p-n junctions and field-effect devices
- Digital logic design: Boolean algebra and combinational circuits
- Basic circuit analysis
Learning outcomes
- Derive MOSFET drain current in linear and saturation regions from device equations
- Design CMOS combinational circuits using complementary logic and verify noise margins
- Draw stick diagrams and apply lambda-based design rules for a given logic gate
- Compute Elmore delay for multi-stage CMOS circuits and identify the critical path
- Calculate dynamic power dissipation for a CMOS gate given switching frequency and load capacitance
- Explain setup and hold time violations and their effect on sequential circuit operation
Modules
Module 1: MOS Device Physics
Topics
- NMOS and PMOS transistor structure and operation
- Threshold voltage and body effect
- MOSFET I-V characteristics in linear and saturation regions
- Short-channel effects and velocity saturation
- SPICE model parameters overview
Article slugs
mosfet-iv-characteristicsthreshold-voltage-body-effectshort-channel-effects-mosfetspice-model-parameters
Lab slug: mosfet-characterization-lab
Module 2: CMOS Logic Design
Topics
- CMOS inverter DC analysis and noise margins
- CMOS NAND, NOR, and complex gate synthesis
- Transmission gate logic
- Dynamic CMOS and domino logic
- Pass transistor logic
Article slugs
cmos-inverter-analysiscmos-nand-nor-gatestransmission-gate-logicdynamic-cmos-domino
Lab slug: cmos-gate-design-lab
Module 3: Layout and Design Rules
Topics
- Lambda-based design rules and layer definitions
- Stick diagrams for CMOS gates
- Latch-up in CMOS and guard rings
- DRC, LVS, and ERC verification concepts
- Area and power estimation from layout
Article slugs
lambda-design-rulesstick-diagrams-cmoslatch-up-guard-ringdrc-lvs-verification
Lab slug: layout-verification-lab
Module 4: Timing and Power
Topics
- Gate delay models and Elmore delay
- Setup time, hold time, and clock skew
- Static timing analysis and critical path
- Dynamic and static power dissipation
- Low-power design techniques
Article slugs
elmore-delay-modelsetup-hold-time-vlsistatic-timing-analysiscmos-power-dissipation
Lab slug: timing-analysis-lab