Applications of Counters in Digital Systems | ECExplain

Visual

Concept overview

A digital counter is a sequential logic circuit that advances through a defined sequence of binary states on each active clock edge. Counters are classified by modulus (the number of distinct states), counting direction (up, down, or up-down), and loading capability (synchronous preset or asynchronous clear). A 4-bit binary counter has modulus 16. Counters built from JK or D flip-flops can be configured for any modulus by decoding a specific terminal count and feeding it back to reset or load inputs. Common ICs include the 74HC163 synchronous 4-bit counter and the 74HC4040 12-bit ripple counter.

Real-world applications

Baud Rate Generation in UART Controllers

Embedded Systems

The STM32F4 UART peripheral uses an internal 16-bit baud rate counter that divides the peripheral clock to generate the precise 16x oversampling clock required for serial framing. For 115200 baud from a 16 MHz clock, the counter reload value is 8.68, split into integer and fractional parts loaded into the BRR register. The fractional part is accumulated to spread timing error across multiple bit periods.

Address Counter in SRAM Controllers

Memory Systems

The ISSI IS61WV51216 SRAM requires sequential addresses for burst read operations. The memory controller in an FPGA uses a 16-bit synchronous counter to generate the address sequence. On each clock cycle, the counter increments and the output drives the address bus. The counter resets to the burst start address on a chip-select assertion, allowing DMA transfers without CPU intervention.

Event Counter in Pulse-Width Modulation Timer

Motor Control / Embedded

The STM32 Timer 1 peripheral uses a 16-bit auto-reload counter running from the APB2 clock. The counter counts up to the ARR register value, generating a PWM period. The CCR register sets the compare match threshold where the output pin toggles. This arrangement drives BLDC motor phases, servo signals, and LED dimming without software intervention once configured.

Frequency Counter in RF Spectrum Analysers

Test and Measurement

Keysight N9030A spectrum analysers use a high-speed prescaler followed by a 32-bit counter to measure the frequency of an unknown signal. The prescaler divides the input frequency by 64 so the counter can operate at a lower clock rate. The counter accumulates pulses over a known gate time of 1 second and the result is the frequency in Hz with sub-hertz resolution.

How it works in practice

A synchronous counter such as the 74HC163 has all flip-flops clocked simultaneously, so there are no intermediate glitch states during counting. The terminal count output (RCO) goes high when the counter reaches 1111 in binary, one clock before it rolls over to 0000. This RCO signal can enable a cascaded counter to increment its own count, building wider counters from 4-bit stages. The synchronous load input (LOAD) allows a preset value to be forced into the counter on the next clock edge, implementing modulo-N counting for any N by loading 0 when count N-1 is detected. The synchronous clear (CLR) in 74HC163 is also clocked, preventing the glitch that would occur with the asynchronous clear of the 74HC161, which resets the counter within the current clock period regardless of the clock edge.

Examples

Modulo-10 Counter Using 74HC163 and NAND Feedback

A 74HC163 counts from 0 to 9 by decoding the state 1010 (decimal 10) using a NAND gate connected to Q3 and Q1. The NAND output drives the synchronous load input. When the counter reaches 1010, the NAND output goes low on the next clock edge, loading 0000 from the preset inputs. The counter then repeats 0000 through 1001, producing a modulo-10 sequence. This avoids the need for a dedicated decade counter IC when one 74HC163 and a single gate are already available on the PCB.

Cascading Two 74HC163s for a 0 to 99 Counter

The units digit 74HC163 has its RCO connected to the ENP input of the tens digit 74HC163. The tens digit counter increments only when the units digit has reached 1111 and RCO is high. Both counters share the same clock. To limit the sequence to 0 to 99, a two-input NAND gate decodes units = 1010 and tens = 1010 simultaneously. Its output drives both LOAD inputs, resetting both counters to 0000 simultaneously on the next clock edge. The resulting 7-segment display output shows decimal 00 through 99 with no software required.

Future scope

Modern SoC peripherals embed 32-bit and 64-bit counters with DMA trigger capabilities, eliminating interrupt overhead for timestamping and measurement. RISC-V cores include a mandatory MCYCLE counter in hardware for performance profiling. Research into stochastic computing explores replacing binary counters with circuits that represent numbers as pulse densities, potentially reducing energy per addition by an order of magnitude for approximate computing tasks in neural network inference accelerators.