PLL Applications in Communication Systems | ECExplain

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Concept overview

A Phase-Locked Loop (PLL) is a feedback control circuit that locks its output oscillator phase and frequency to a reference input signal. The loop consists of a phase detector, a low-pass loop filter, and a voltage-controlled oscillator (VCO). Once locked, the PLL tracks frequency deviations in the input, making it useful wherever a clean, stable, or synthesised frequency is needed from a potentially noisy or drifting source.

Real-world applications

FM Radio Demodulation

Consumer Electronics

In FM receivers such as the LM565 PLL IC, the VCO tracks the instantaneous frequency of the received FM signal. The correction voltage applied to the VCO directly reproduces the original audio baseband signal without requiring a discriminator transformer.

Clock Recovery in Serial Links

Computer Hardware

High-speed serial interfaces including PCIe, SATA, and USB 3.x embed clock information in the data stream. A PLL in the receiver, such as those integrated into CDR blocks in Xilinx UltraScale FPGAs, extracts a clean clock aligned to the incoming bit transitions.

Frequency Synthesis in RF Transceivers

Wireless Communications

The Qualcomm QRF5550 and similar RF front-end modules use integer-N and fractional-N PLLs to generate the local oscillator frequencies required for channel selection across LTE and 5G NR bands, replacing banks of fixed crystals with a single reference and programmable divider.

How it works in practice

In a frequency synthesiser application, the PLL reference input connects to a stable crystal oscillator, typically at 10 MHz or 12.8 MHz. The feedback path includes a programmable integer or fractional divider set to value N. The phase detector compares the divided-down VCO output with the reference; any phase error produces a proportional DC error voltage after the loop filter. This voltage steers the VCO until the divided output matches the reference frequency, locking the output at N times the reference. The loop filter bandwidth determines how quickly the loop acquires lock and how much reference spurs appear at the output. Narrow bandwidths suppress spurs but slow acquisition; wider bandwidths lock faster but pass more phase noise from the reference and charge pump. In clock data recovery, the phase detector is replaced by a bang-bang or linear detector that samples data transitions, and the loop continuously re-centres the sampling point to minimise bit errors.

Examples

LM565 PLL as FM Demodulator

The LM565 has an internal VCO with a free-running frequency set by an external RC network. When an FM signal enters pin 2, the phase detector output drives the VCO through pin 7. Once locked, the demodulated audio appears at pin 7 with a sensitivity of approximately 0.2 V per kHz deviation. A 10 nF capacitor on pin 7 forms the low-pass loop filter that sets the audio bandwidth.

Fractional-N Synthesis for 5G NR

A 5G NR radio unit must tune to channel rasters spaced 15 kHz or 30 kHz apart in FR1 bands from 600 MHz to 7.125 GHz. An integer-N PLL with a 12.8 MHz reference cannot resolve steps that small without lowering the reference frequency to 15 kHz, which degrades phase noise severely. A fractional-N PLL with a delta-sigma modulator dithers the divider value between N and N+1 on a cycle-by-cycle basis, producing a time-averaged non-integer ratio. This allows fine frequency resolution while keeping the reference at 12.8 MHz and the loop bandwidth wide enough for low noise.

Future scope

All-digital PLLs (ADPLLs) are replacing analogue loop filters in advanced CMOS nodes below 7 nm because passive RC components do not scale well. MediaTek and Intel have taped out ADPLLs where the phase detector, loop filter, and DCO are entirely digital, enabling reconfigurability through firmware and eliminating sensitivity to supply voltage variation. Sub-sampling PLLs that compare VCO output directly to the reference at sub-harmonic rates reduce the contribution of phase detector noise and are an active area in IEEE JSSC publications. In optical coherent receivers, carrier-phase estimation PLLs operating at symbol rates above 100 Gbaud are being implemented in DSP silicon rather than analogue hardware.