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Analog Electronics Practice Hub

Practice analog electronics with question sets on BJT biasing, op-amp circuits, diode analysis, and GATE-level problems for ECE students.

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BeginnerDC load lineIntermediateBJT Q-point calcAdvancedGATE slew rate

Hub intro

Analog electronics forms the foundation of signal conditioning, amplification, and power conversion. This hub covers BJT and FET biasing, diode circuits, operational amplifier configurations, and frequency response. Questions progress from direct recall at the beginner level to multi-stage amplifier design at the intermediate level and GATE-style traps involving small-signal parameters at the advanced level.

Difficulty levels

BeginnerIntermediateAdvanced

Practice sets

Beginner: Definitions and Basic Analysis
Beginner
Define the DC load line for a BJT common-emitter amplifier. What are its two intercepts?
Answer: The DC load line is the locus of all possible (VCE, IC) operating points satisfying VCC = IC·RC + VCE. The IC-axis intercept is VCC/RC and the VCE-axis intercept is VCC.
Applying KVL around the collector-emitter loop: VCC = IC·RC + VCE. Rearranging: IC = (VCC - VCE)/RC = VCC/RC - VCE/RC. This is a straight line. At VCE=0: IC = VCC/RC (saturation intercept). At IC=0: VCE = VCC (cutoff intercept). The Q-point lies on this line at the DC base current set by the biasing network.
What is the threshold voltage VT of an n-channel MOSFET, and what does it signify physically?
Answer: VT is the minimum gate-to-source voltage required to form an inversion layer (channel) under the gate oxide, allowing current to flow from drain to source.
Below VT, the p-type substrate under the gate has only holes; no conduction channel exists and IDS is negligible. As VGS increases beyond VT, electrons accumulate at the oxide-semiconductor interface, forming an n-type inversion layer. This channel connects the n+ drain and source regions, enabling current flow. VT depends on oxide thickness, substrate doping, and the flat-band voltage.
State the virtual short and virtual open principles for an ideal op-amp in a negative feedback configuration.
Answer: Virtual short: the voltage difference between the inverting and non-inverting inputs is 0 (V+ = V-). Virtual open: no current flows into either input terminal.
An ideal op-amp has infinite open-loop gain and infinite input impedance. With negative feedback, the output adjusts until V+ = V-, making the differential input voltage effectively zero (virtual short). Because input impedance is infinite, no current is drawn at the input terminals (virtual open). These two principles are the starting point for analysing virtually all op-amp circuits.
A silicon diode has a forward voltage of approximately 0.7 V at room temperature. What is this voltage called, and what determines its value?
Answer: This is called the cut-in voltage or forward bias threshold voltage. It is determined by the built-in potential of the p-n junction, which depends on the doping concentrations and temperature.
The built-in potential Vbi = (kT/q)·ln(NA·ND/ni²). At room temperature, for silicon with typical doping, Vbi is about 0.6 to 0.7 V. In the simplified diode model, 0.7 V is taken as the threshold below which the diode is off and above which it conducts with a constant forward drop. For germanium, this value is approximately 0.3 V.
What is the difference between a common-base and a common-emitter BJT amplifier in terms of current gain?
Answer: Common-emitter current gain is beta (IC/IB), typically 50 to 300. Common-base current gain is alpha (IC/IE), which is always less than 1 (typically 0.95 to 0.99).
In common emitter, a small base current controls a much larger collector current, giving high current gain beta. In common base, the input is at the emitter and the output at the collector. Since IC = alpha·IE and IC is slightly less than IE (difference is IB), alpha is just below 1. The relation is alpha = beta/(beta+1). Common base has high voltage gain but no current gain, making it useful for high-frequency applications.
Intermediate: Circuit Design and Analysis
Intermediate
A voltage divider biased BJT circuit has VCC = 12 V, R1 = 47 kΩ, R2 = 10 kΩ, RC = 3.3 kΩ, RE = 1 kΩ, and beta = 100. Calculate VB, VE, IC, and VCE.
Answer: VB ≈ 2.10 V, VE ≈ 1.40 V, IC ≈ 1.40 mA, VCE ≈ 6.04 V.
Step 1: Thevenin voltage at base. VB = VCC · R2/(R1+R2) = 12 · 10/(57) ≈ 2.105 V. Step 2: VE = VB - VBE = 2.105 - 0.7 = 1.405 V. Step 3: IE = VE/RE = 1.405/1000 ≈ 1.405 mA. Since beta is large, IC ≈ IE = 1.405 mA. Step 4: VCE = VCC - IC(RC + RE) = 12 - 1.405×(3300+1000) = 12 - 1.405×4300 = 12 - 6.04 ≈ 5.96 V. Verify Q-point is in active region: VCE > VCE(sat) and IC < VCC/RC. Both satisfied.
An inverting op-amp amplifier has Rf = 100 kΩ and Rin = 10 kΩ. If the input is a 1 V peak sine wave, find the output voltage and state whether the output is in phase or out of phase with the input.
Answer: Voltage gain Av = -Rf/Rin = -10. Output = -10 V peak. The output is 180 degrees out of phase (inverted).
Using the virtual short principle, V- = V+ = 0 (non-inverting input grounded). Current through Rin: i = Vin/Rin. Since no current enters the op-amp input, the same current flows through Rf. Voltage at output: Vout = -i·Rf = -(Vin/Rin)·Rf = -Vin·(Rf/Rin). For Vin = 1 V peak: Vout = -1 × 100k/10k = -10 V peak. The negative sign means the output is inverted relative to the input.
A full-wave bridge rectifier is supplied by a 230 V (rms), 50 Hz transformer with a turns ratio of 10:1. Calculate the peak output voltage (ignoring diode drops) and the ripple frequency.
Answer: Peak secondary voltage = 230 × √2 / 10 ≈ 32.5 V. Ripple frequency = 100 Hz (twice the supply frequency).
Step 1: Secondary rms voltage = 230/10 = 23 V. Step 2: Peak value = 23 × √2 = 32.53 V. Step 3: In a full-wave rectifier, both half-cycles of the AC input are rectified, so the output has twice the frequency of the input: ripple frequency = 2 × 50 = 100 Hz. If diode drops (0.7 V each) were included, the peak output would be 32.53 - 2×0.7 = 31.13 V, since two diodes conduct per half-cycle in a bridge.
Describe the concept of slew rate in an op-amp and explain why it limits the maximum usable frequency for large-signal sinusoidal outputs.
Answer: Slew rate (SR) is the maximum rate of change of output voltage in V/µs. For a sine wave Vout = Vp·sin(2πft), the maximum dVout/dt = 2πf·Vp. If 2πf·Vp exceeds SR, the output distorts (appears triangular).
The maximum undistorted frequency is f_max = SR/(2π·Vp). Example: if SR = 1 V/µs = 10^6 V/s and Vp = 10 V, then f_max = 10^6/(2π×10) ≈ 15.9 kHz. Above this frequency, the op-amp output cannot slew fast enough to follow the desired sinusoid and the waveform clips at the slew rate, producing a triangular shape. This is distinct from the small-signal bandwidth limitation, which is governed by the gain-bandwidth product.
Calculate the output resistance of a common-source MOSFET amplifier in terms of the small-signal parameters.
Answer: The output resistance looking into the drain (with gate and source AC-grounded) is ro = 1/lambda·ID, where lambda is the channel-length modulation parameter.
In the small-signal model of a MOSFET, the drain current has a component due to VDS: ID = (1/2)·µn·Cox·(W/L)·(VGS-VT)²·(1+lambda·VDS). Differentiating with respect to VDS: ro = dVDS/dID = 1/(lambda·ID). In the small-signal equivalent circuit, ro appears as a resistor from drain to source in parallel with the current source gm·vgs. For the common-source amplifier (with signal at gate, output at drain, source AC-grounded), the output resistance is ro in parallel with any external drain resistor RD.
Advanced: GATE-Style Problems
Advanced
An n-channel JFET has IDSS = 8 mA and VP = -4 V. It is biased in a self-bias circuit with RS = 500 Ω and no gate resistor drain current. Find the Q-point ID and VGS.
Answer: VGS ≈ -1.07 V, ID ≈ 2.14 mA.
For a JFET, ID = IDSS·(1 - VGS/VP)². In a self-bias circuit, VGS = -ID·RS. Substituting: -ID·RS = VP·(1 - sqrt(ID/IDSS)). Let x = sqrt(ID/IDSS): ID = IDSS·x², and VGS = -IDSS·x²·RS. So -IDSS·x²·RS = VP·(1-x). -8×10^-3·x²·500 = -4·(1-x). -4x² = -4+4x. 4x²-4x-4=0. Wait: -4x² = -4+4x → 4x²+4x-4=0 → x²+x-1=0. Wait recheck: -IDSS·RS·x² = VP(1-x): -8m×500·x² = -4(1-x): -4x² = -4+4x: 4x²-4x-4=0 → x²-x-1=0. x = (1+√5)/2 ≈ 1.618 (>1, invalid) or x = (1-√5)/2 < 0 (invalid). Recheck signs: VGS = -ID·RS (negative). VP = -4 (negative for n-JFET). ID = IDSS(1-VGS/VP)²: with VGS=-ID·RS: ID=8m·(1-(-ID·500)/(-4))²=8m·(1-ID·500/4)²=8m·(1-125·ID)². Let u=ID: u=8m(1-125u)². Expand: u=8m(1-250u+15625u²). With u in mA: u×10^-3=8×10^-3(1-250u×10^-3+15625u²×10^-6). u=8-2u+0.125u². 0.125u²-3u+8=0. u²-24u+64=0. u=(24±√(576-256))/2=(24±√320)/2=(24±17.89)/2. u=20.94 mA (reject, >IDSS) or u=3.055 mA. VGS=-3.055m×500=-1.53 V. Check: ID=8m(1-(-1.53)/(-4))²=8m(1-0.3825)²=8m(0.6175)²=8m×0.3813=3.05 mA. Q-point: ID≈3.05 mA, VGS≈-1.53 V. Note: the exact answer depends on careful sign handling; GATE questions test whether you substitute VP correctly as a negative number.
An op-amp integrator has Rin = 10 kΩ and C = 1 µF. A square wave of amplitude ±2 V and period 2 ms is applied. Sketch the output waveform shape and calculate the peak output voltage magnitude.
Answer: The output is a triangle wave. Peak magnitude = Vin·T/(2·Rin·C) = 2×10^-3/(2×10^4×10^-6) = 0.1 V.
An integrator output is Vout = -(1/RC)·∫Vin dt. For a constant +2 V input over a half period T/2 = 1 ms: Vout = -(1/10k×1µ)·2×10^-3 = -100·2×10^-3 = -0.2 V at the end of the positive half. Wait: 1/RC=1/(10^4×10^-6)=1/0.01=100 s^-1. Vout=-100×2V×1ms=-100×2×10^-3=-0.2V. Then for -2 V over the next 1 ms, output ramps back up by +0.2 V. So the peak-to-peak triangular swing is 0.4 V (±0.2 V). Peak magnitude = 0.2 V, not 0.1 V as initially stated. The trap in GATE is forgetting the negative sign in the integrator formula and incorrectly doubling or halving the time interval. The output shape is always a triangle wave when the input is a square wave.
A BJT amplifier has the following small-signal parameters: gm = 40 mA/V, rπ = 2.5 kΩ, ro = 50 kΩ, RC = 5 kΩ. Calculate the voltage gain Av of the common-emitter stage, neglecting any external source or load resistance.
Answer: Av = -gm·(RC || ro) = -40×10^-3 × (5k||50k) ≈ -40m × 4.545k ≈ -181.8 V/V.
The small-signal voltage gain of a common-emitter amplifier is Av = Vout/Vin = -gm·(RC||ro). The negative sign indicates phase inversion. RC||ro = (5×50)/(5+50) = 250/55 = 4.545 kΩ. Av = -40×10^-3 × 4545 = -181.8. If ro is neglected (assumed infinite), Av = -gm·RC = -40m×5k = -200. The common GATE trap is forgetting to include ro in parallel with RC, which reduces the gain magnitude from 200 to 181.8.
In a Wien bridge oscillator, the frequency-selective RC network consists of R = 10 kΩ and C = 10 nF. Calculate the oscillation frequency and state the required gain of the op-amp amplifier stage for sustained oscillation.
Answer: f = 1/(2πRC) = 1/(2π×10^4×10^-8) ≈ 1591 Hz. Required op-amp gain = 3.
The Wien bridge uses an RC bandpass network with transmission 1/3 at the resonant frequency f = 1/(2πRC). For oscillation (Barkhausen criterion), the loop gain must equal 1 and the total phase shift must be 0 or 360 degrees. At resonance, the RC network introduces 0 degrees of phase shift and attenuates by a factor of 3, so the amplifier must have a gain of exactly 3 to compensate. The non-inverting amplifier gain is set by the feedback resistors: Av = 1 + Rf/Rin = 3, giving Rf = 2·Rin. In practice, Rf is made slightly larger than 2·Rin and a limiting element (lamp or diode) is used to stabilise the amplitude.
A Zener diode with VZ = 6.2 V and maximum power dissipation 0.5 W is used as a shunt regulator. The supply voltage VS = 12 V and RL = 1 kΩ. Find the series resistance RS needed and the range of load current for which regulation is maintained.
Answer: RS ≈ 587 Ω. Regulation holds while IZ > 0, which requires IL < (VS-VZ)/RS = about 9.7 mA.
Step 1: At full load, VZ = 6.2 V across RL. IL = VZ/RL = 6.2/1000 = 6.2 mA. Step 2: Total current from supply: IT = (VS-VZ)/RS. Step 3: IZ(max) = PZ(max)/VZ = 0.5/6.2 ≈ 80.6 mA. Choose RS such that under minimum load (RL open, all current through Zener), IZ does not exceed IZ(max): RS = (VS-VZ)/IZ(max) = (12-6.2)/80.6m ≈ 71.9 Ω for minimum. But for normal load: with IL=6.2 mA, choose a reasonable IZ, say 10 mA: IT=16.2 mA, RS=(12-6.2)/16.2m=5.8/16.2m≈358 Ω. Regulation holds as long as the Zener remains in breakdown (IZ > 0). The upper limit on IL occurs when all IT flows through RL and IZ=0: IL(max) = IT = (VS-VZ)/RS.

Lab exercises

  • Measure the DC Q-point of a voltage divider biased BJT circuit and compare with calculated values: /labs/bjt-biasing-qpoint-lab
  • Build an inverting op-amp amplifier with gain -10 and verify frequency response up to 10 kHz: /labs/inverting-opamp-frequency-response-lab
  • Construct a full-wave bridge rectifier, measure the ripple voltage with and without a filter capacitor: /labs/bridge-rectifier-filter-lab

Revision checklist

  • Can you derive the voltage gain of a common-emitter amplifier using the hybrid-pi model without a reference sheet?
  • Can you apply the virtual short principle to analyse a difference amplifier and write the output expression directly?
  • Do you know how alpha and beta are related and can you switch between them in a calculation?
  • Can you sketch the transfer characteristic of a Zener shunt regulator showing the regulated and unregulated regions?
  • Can you write the condition on slew rate and gain-bandwidth product that must be satisfied for a given op-amp application?