ECExplain

Practice hubs

Digital Electronics Practice Hub

Practice digital electronics with structured question sets covering combinational logic, sequential circuits, and GATE-level problems for ECE students.

Visual

BeginnerDefine XNOR gateIntermediateDesign 3-bit counterAdvancedGATE mux trap

Hub intro

This hub organises digital electronics practice into three difficulty tiers. Beginner questions test your recall of definitions and truth tables. Intermediate questions require you to design or analyse multi-stage circuits. Advanced questions are modelled on GATE patterns and include common traps around timing, hazards, and minimisation edge cases.

Difficulty levels

BeginnerIntermediateAdvanced

Practice sets

Beginner: Definitions and Basic Logic
Beginner
What is the Boolean expression for a 2-input XNOR gate, and what does it evaluate to when both inputs are 1?
Answer: Y = A XNOR B = AB + A'B'. When A = 1 and B = 1, Y = 1.
XNOR produces a 1 when both inputs are equal. For A=1, B=1: AB = 1·1 = 1, and A'B' = 0·0 = 0, so Y = 1 + 0 = 1. This is the complement of XOR, which outputs 1 only when inputs differ.
Define a half adder. Write its sum and carry expressions.
Answer: A half adder adds two single bits A and B. Sum = A XOR B, Carry = AB.
The sum bit uses XOR because 1+1 in binary produces a sum of 0 (with a carry), while 1+0 or 0+1 produces a sum of 1. The carry bit uses AND because a carry of 1 is generated only when both inputs are 1. A half adder cannot handle a carry-in from a previous stage; that is the role of a full adder.
How many rows does the truth table of a 3-variable Boolean function contain, and why?
Answer: 8 rows, because 3 binary variables produce 2^3 = 8 distinct input combinations.
Each of the 3 variables (A, B, C) can independently be 0 or 1, giving 2 choices per variable. The total number of combinations is 2 × 2 × 2 = 8. Generalising, an n-variable function has 2^n rows. For n=3: 2^3 = 8.
What is the difference between a latch and a flip-flop?
Answer: A latch is level-triggered and changes state while the enable or clock signal is at a specified level. A flip-flop is edge-triggered and changes state only on the rising or falling edge of the clock.
In a latch, the output can follow the input throughout the entire period when the enable is high (transparent phase). In a flip-flop, the output is updated only at the precise clock edge, which makes timing analysis easier and predictable. Most synchronous sequential circuits use flip-flops for this reason.
State De Morgan's theorems.
Answer: (A + B)' = A' · B' and (A · B)' = A' + B'.
The first theorem says the complement of a sum equals the product of the complements. The second says the complement of a product equals the sum of the complements. These are essential for converting between NOR and NAND implementations and for simplifying Boolean expressions. Verify by truth table: for A=1, B=0, (A+B)' = (1)' = 0, and A'·B' = 0·1 = 0. Consistent.
Intermediate: Circuit Design and Analysis
Intermediate
Minimise the Boolean function F(A,B,C,D) = Σm(0,1,2,5,8,9,10) using a Karnaugh map and write the simplified SOP expression.
Answer: F = A'C' + A'BD' + AB'C'
Plot the minterms on a 4-variable K-map. Group minterm 0,1,8,9 (A'C' covers 0,1,2 and 8,9,10 partially). Recheck groupings: {0,1,8,9} form a valid quad giving A'C' (A and C both 0, B and D free? No — check: m0=0000, m1=0001, m8=1000, m9=1001 — A varies, so incorrect quad). Correct approach: {0,2,8,10} give B'D' (B=0, D=0 across all four). {0,1} give A'B'C'. {5} pairs with {1} giving A'BD'. Final minimised form: F = B'D' + A'B'C' + A'BD'. Always verify each group covers only plotted minterms and has a size of 1, 2, 4, or 8.
Design a 3-bit synchronous up-counter using JK flip-flops. Write the excitation equations for J and K inputs of each flip-flop.
Answer: For Q0 (LSB): J0 = K0 = 1. For Q1: J1 = K1 = Q0. For Q2 (MSB): J2 = K2 = Q0·Q1.
A synchronous up-counter increments by 1 on each clock edge. Q0 toggles every clock cycle, so J0=K0=1 (JK toggle mode). Q1 toggles only when Q0=1, so J1=K1=Q0. Q2 toggles only when both Q0 and Q1 are 1, so J2=K2=Q0·Q1. Derive these from the JK excitation table: if Q goes 0→1, J=1 K=X; if 1→0, J=X K=1; if no change, J=0 K=X. Map next-state transitions from the count sequence and read off each J and K expression.
A combinational circuit has the Boolean output F = AB + BC + CA. Identify all static-1 hazards and state how to eliminate them.
Answer: There is a static-1 hazard on the transition A: 1→0 when B=1 and C=1. Eliminate by adding the consensus term BC.
A static-1 hazard occurs when the output momentarily drops to 0 during a transition that should keep it at 1. On the K-map, adjacent 1-cells not covered by a common group can produce a glitch. For F = AB + BC + CA, the pairs AB and CA share the minterm ABC (A=1,B=1,C=1). When A transitions from 1 to 0, the AB term turns off before CA can respond, causing a brief 0. Adding the consensus term BC bridges this gap, giving F = AB + BC + CA + BC = AB + BC + CA. The redundant BC term ensures continuity.
What is the modulus of a ripple counter built with 4 JK flip-flops, and what is the maximum toggle frequency of the LSB flip-flop if the clock frequency is 16 MHz?
Answer: Modulus = 2^4 = 16. The LSB flip-flop toggles at the clock frequency, so its toggle frequency is 16 MHz.
A ripple counter with n flip-flops counts from 0 to 2^n - 1, so its modulus (number of states) is 2^n. For 4 flip-flops, modulus = 16. In a ripple counter, Q0 (LSB) toggles on every clock pulse, giving a toggle rate equal to the clock frequency. Q1 toggles at half the clock rate, Q2 at one-quarter, and Q3 at one-eighth. So at 16 MHz clock: Q0 toggles at 16 MHz, Q1 at 8 MHz, Q2 at 4 MHz, Q3 at 2 MHz.
Convert the hexadecimal number 2AF to binary and then to BCD.
Answer: 2AF (hex) = 0010 1010 1111 (binary) = 0110 0111 (BCD for decimal 687).
Step 1: Convert each hex digit to 4-bit binary. 2 = 0010, A = 1010, F = 1111. So 2AF = 0010 1010 1111 in binary. Step 2: Convert binary to decimal. 2AF hex = 2×256 + 10×16 + 15 = 512 + 160 + 15 = 687 decimal. Step 3: Encode each decimal digit in BCD. 6 = 0110, 8 = 1000, 7 = 0111. BCD = 0110 1000 0111. Note that BCD encodes each decimal digit separately and is not the same as straight binary.
Advanced: GATE-Style Problems
Advanced
A 4-to-1 multiplexer has select lines S1 (MSB) and S0 (LSB) and data inputs I0, I1, I2, I3. If I0 = A, I1 = A', I2 = B, I3 = 0, and select inputs are S1 = B, S0 = A, what is the output Y expressed as a minimal Boolean function of A and B?
Answer: Y = AB' + A'B = A XOR B.
The multiplexer output is Y = I0·S1'·S0' + I1·S1'·S0 + I2·S1·S0' + I3·S1·S0. Substituting: Y = A·B'·A' + A'·B'·A + B·B·A' + 0·B·A. Term 1: A·B'·A' = 0 (A·A'=0). Term 2: A'·B'·A = 0 (A·A'=0). Wait, recalculate: S1=B, S0=A. Y = A·(B)'·(A)' + A'·(B)'·(A) + B·(B)·(A)' + 0. = A·B'·A' + A'·B'·A + B²·A'. Since B²=B: = 0 + 0 + B·A'. That gives Y = A'B. Recheck input mapping: I0 connected to S1=0,S0=0 output active when B=0,A=0. Y = A·[B'A'] + A'·[B'A] + B·[BA'] + 0·[BA] = AB'A' + A'AB' + BB·A' = 0 + 0 + BA'. So Y = A'B. The trap here is assuming XOR; the actual answer is A'B because S0=A and S1=B, so only minterm S1=1,S0=0 (B=1,A=0) is active via I2=B=1.
In a clocked SR flip-flop, the forbidden state occurs when S=1 and R=1. If an SR flip-flop is converted to a D flip-flop by connecting D to S and D' to R, what happens at the output when D transitions from 0 to 1 and the clock is high?
Answer: The output Q follows D: Q goes to 1. The forbidden state is never reached because S and R are complementary.
In the D-to-SR conversion, S = D and R = D'. Since D and D' are always complements, S and R can never both be 1 simultaneously. When D=0: S=0, R=1, so Q=0 (reset state). When D=1: S=1, R=0, so Q=1 (set state). The common trap in GATE problems is to think the transition D: 0→1 passes through S=1,R=1 at some intermediate instant. In a clocked flip-flop, the inputs are sampled at the clock edge; intermediate logic glitches during input transitions do not affect the stored state. The output reliably follows D.
A Johnson counter (twisted-ring counter) is built with 4 D flip-flops. How many valid states does it have, and what is its modulus? If the counter enters an invalid state, describe what happens.
Answer: Valid states = 2×n = 2×4 = 8. Modulus = 8. Invalid states: the counter may lock into a sub-cycle of invalid states and never return to the valid sequence without a reset.
A Johnson counter with n flip-flops has 2n valid states from the sequence where the complement of the MSB output is fed back to the input of the LSB flip-flop. For n=4, the 8 valid states are 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, then back to 0000. The remaining 2^4 - 8 = 8 states are invalid. In practice, if power-on initialisation lands in an invalid state, the counter can enter a closed loop of invalid states, never recovering the correct sequence. A self-correcting Johnson counter adds logic to detect invalid states and force a return to the valid cycle. GATE questions often ask you to identify this lockup condition.
For the Boolean function F = Σm(1,3,5,7,9,11,13,15) of four variables A, B, C, D, find the minimised SOP and comment on the implementation cost compared to a single gate.
Answer: F = D. The function is 1 whenever D=1, regardless of A, B, C.
Plot all 16 minterms. Those where F=1 are: 1(0001), 3(0011), 5(0101), 7(0111), 9(1001), 11(1011), 13(1101), 15(1111). In every minterm, D=1. A, B, and C take all possible combinations while D remains 1. Therefore F = D, implemented by a single wire with no gates. A common GATE trap is to over-minimise using K-map groups and miss that all F=1 minterms share a single literal. The lesson: always check whether the entire on-set can be covered by a single literal before drawing groups.
A synchronous sequential circuit has next-state equations: Q1(t+1) = Q1'(t)·Q0(t) + Q1(t)·Q0'(t) and Q0(t+1) = Q1'(t)·Q0'(t). Starting from state Q1Q0 = 00, trace the state sequence for 4 clock pulses.
Answer: State sequence: 00 → 01 → 10 → 00 → 01 ... (modulo-3 counter cycling through 00, 01, 10).
From Q1Q0=00: Q1(t+1)=1'·0+0·1'=0+0=0, wait: Q1'=1,Q0=0: Q1(t+1)=1·0+0·1=0. Q0(t+1)=1·1=1. Next state: 01. From Q1Q0=01: Q1'=1,Q0=1,Q1=0,Q0'=0. Q1(t+1)=1·1+0·0=1. Q0(t+1)=1·0=0. Next state: 10. From Q1Q0=10: Q1'=0,Q0=0,Q1=1,Q0'=1. Q1(t+1)=0·0+1·1=1. Wait: Q0=0, so Q1(t+1)=0·0+1·1=1. Q0(t+1)=Q1'·Q0'=0·1=0. Next state: 10 again? Recheck: Q1=1,Q0=0: Q1(t+1)=Q1'Q0+Q1Q0'=0·0+1·1=1. Q0(t+1)=Q1'Q0'=0·1=0. So 10→10, which means the sequence locks. Corrected sequence from 00: 00→01→10→10(lock). The state 11 is unreachable. This is a GATE-style trap: state 10 is a self-loop, not part of a 3-cycle. Always complete the full state table before concluding modulus.

Lab exercises

  • Complete the half adder and full adder circuit on breadboard and verify truth table: /labs/half-adder-full-adder-lab
  • Build a 3-bit ripple counter using JK flip-flops and observe waveforms on an oscilloscope: /labs/3-bit-ripple-counter-lab
  • Implement a 4-variable K-map minimisation and verify the simplified circuit output against the original truth table: /labs/kmap-minimisation-verification-lab

Revision checklist

  • Can you write the truth table for a 3-input majority function from scratch and derive its minimal SOP?
  • Can you draw the state diagram of a 3-bit synchronous up-counter from memory, including the state transitions?
  • Can you identify and correct a static-1 hazard in a given two-level AND-OR circuit?
  • Do you know when a JK flip-flop is in toggle mode versus set mode versus reset mode?
  • Can you convert between Gray code and binary for any 4-bit number without a lookup table?
  • Do you know the difference between the modulus of a Johnson counter and that of a ring counter with the same number of flip-flops?