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Microprocessors Practice Hub

Practice questions for Microprocessors covering 8085 architecture, instruction sets, memory interfacing, and interrupt handling for GATE ECE.

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Beginner8085 RegistersIntermediateMemory DecodingAdvancedInterrupt Priority

Hub intro

This hub covers the 8085 and 8086 microprocessor architecture, instruction execution, memory and I/O interfacing, interrupt structures, and assembly-level programming. Build your understanding from pin-level definitions up to timing diagram analysis and interrupt priority problems.

Difficulty levels

BeginnerIntermediateAdvanced

Practice sets

Beginner: Definitions and Direct Formulas
Beginner
Name the registers in the 8085 microprocessor and state the width of each.
Answer: Accumulator (A): 8-bit. General purpose registers B, C, D, E, H, L: 8-bit each, can be paired as BC, DE, HL for 16-bit use. Program Counter (PC): 16-bit. Stack Pointer (SP): 16-bit. Temporary registers W and Z: 8-bit (internal, not programmer-accessible).
The 8085 has a 16-bit address bus (64 KB addressable memory) and an 8-bit data bus. The flag register F is paired with A to form the PSW (Program Status Word). Flags include Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), and Carry (CY). The HL pair is the most frequently used for memory addressing via indirect addressing mode.
What is the function of the ALE (Address Latch Enable) signal in the 8085?
Answer: ALE is a signal that goes high during the first clock cycle (T1) of a machine cycle to indicate that the lower 8 bits of the address (A7-A0) are present on the multiplexed AD7-AD0 bus. An external latch (such as the 8212 or 74LS373) uses ALE to capture and hold this address before the bus switches to carry data.
The 8085 multiplexes the lower address byte and the data byte on the same 8 pins (AD7-AD0) to reduce pin count. Without an external latch triggered by ALE, the lower address byte would be lost once the bus transitions to data. The upper address byte (A15-A8) is available on dedicated pins and does not need latching.
What is the difference between IN and MOV instructions in 8085 assembly?
Answer: IN port_address reads an 8-bit value from the specified I/O port into the accumulator. MOV dst, src copies data between registers or between a register and memory. IN is for I/O space access; MOV does not involve I/O ports.
The 8085 uses isolated I/O, meaning I/O ports have a separate address space from memory (256 ports, addressed 00H to FFH). The IN instruction asserts IO/M' high to distinguish I/O access from memory access. Memory-mapped I/O uses regular memory instructions (LDA, STA, MOV) to access peripheral registers placed in the memory address space.
Intermediate: Multi-step Problems
Intermediate
An 8085 system uses a 2 MHz clock. Calculate the time for one machine cycle T-state and the duration of a memory read operation (4 T-states).
Answer: Clock period = 1 / 2 × 10^6 = 0.5 μs per T-state. Memory read = 4 T-states × 0.5 μs = 2 μs.
The 8085 clock period is 1/f. A T-state is one clock period. Basic machine cycles: opcode fetch = 4 T-states, memory read/write = 3 T-states (though the question states 4, which applies to opcode fetch). WAIT states can be inserted by slow memory to stretch the cycle. At 2 MHz, one instruction cycle is 1 to several machine cycles depending on the instruction.
An 8085 system has 4 KB of ROM starting at 0000H and 2 KB of RAM starting at 2000H. Determine the address range occupied by each and identify one decoding method.
Answer: ROM: 0000H to 0FFFH (4096 bytes = 4 KB). RAM: 2000H to 27FFH (2048 bytes = 2 KB). A simple decoding method is linear select: use A12 to select ROM (A12 = 0) and A13 to select RAM (A13 = 1) for the target ranges.
4 KB requires 12 address lines (A11-A0). Address range = 4096 locations starting at 0000H ends at 0FFFH. 2 KB requires 11 address lines (A10-A0). Starting at 2000H (binary: 0010 0000 0000 0000), the range ends at 2000H + 7FFH = 27FFH. Linear select decoding is simple but leaves aliased addresses where the chip responds to more than one address. Full decoding using a 3-to-8 decoder (74LS138) eliminates aliasing.
Write an 8085 assembly subroutine that adds two 8-bit numbers stored at memory addresses 2050H and 2051H and stores the result at 2052H.
Answer: LDA 2050H ; Load first number into A MOV B, A ; Copy to B LDA 2051H ; Load second number into A ADD B ; A = A + B STA 2052H ; Store result RET
LDA loads the accumulator from a direct 16-bit address. MOV B, A saves the first operand because LDA overwrites A. ADD B adds register B to the accumulator. STA stores A to the 16-bit direct address. If the sum exceeds FFH, the Carry flag (CY) is set but the stored byte is only the lower 8 bits. For a 16-bit result, check CY after ADD and store 01H at 2053H if CY is set.
Advanced: GATE-style Questions
Advanced
In an 8085 system, the instruction MVI A, 32H is stored at address 1000H. What is the content of the PC after the opcode fetch machine cycle? After the full instruction execution?
Answer: After opcode fetch: PC = 1001H. After full execution: PC = 1002H. MVI A is a 2-byte instruction (opcode at 1000H, operand 32H at 1001H). The PC increments to 1001H after the opcode fetch and to 1002H after the operand fetch.
The trap is to increment PC by 2 immediately or to forget that PC updates once per byte fetched. MVI A, data is a 2-byte instruction: byte 1 is the opcode (3EH), byte 2 is the immediate data. During T1 of the opcode fetch cycle, PC = 1000H is placed on the address bus, then PC increments to 1001H. During the operand fetch (second machine cycle), 1001H is placed on the bus, then PC increments to 1002H. Execution of the MOV action does not increment PC further.
The 8085 has five interrupt inputs: TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. List them in decreasing priority order and state which are maskable.
Answer: Priority order (highest to lowest): TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR. TRAP is non-maskable. RST 7.5, RST 6.5, RST 5.5, and INTR are maskable via the SIM instruction and the Interrupt Enable flip-flop (EI/DI instructions).
TRAP is the highest priority, edge-and-level triggered, and cannot be masked. This makes it suitable for power failure detection. RST 7.5 is edge-triggered; a pending RST 7.5 is latched internally even if the signal goes low. RST 6.5 and RST 5.5 are level-triggered and must be held high until acknowledged. INTR is the general-purpose vectored interrupt using an external interrupt controller (8259A) to supply the restart address.

Lab exercises

  • Write and simulate an 8085 program to sort a 10-element array in ascending order using GNUSim8085 or sim8085.com: lab-8085-sort-program
  • Interface a 7-segment display to an 8085 kit and write the multiplexing routine to display a 4-digit number: lab-7seg-8085-interface
  • Configure the 8259A PIC to handle three interrupt levels and verify priority resolution on the 8086 trainer kit: lab-8259a-interrupt-controller

Revision checklist

  • Can you draw the 8085 flag register bit positions and state the condition that sets each flag?
  • Can you trace through the opcode fetch and memory read machine cycles on a timing diagram, showing ALE, RD, WR, and the AD0-AD7 bus?
  • Can you decode a memory map for a system with 8 KB ROM and 4 KB RAM using a 74LS138 decoder?
  • Can you state the vector address for each of the five 8085 interrupts from memory?
  • Can you identify addressing modes (immediate, register, direct, indirect) in a given sequence of 8085 instructions?
  • Can you write the 8085 code to perform 16-bit addition using register pairs?