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Hub intro
This hub covers CMOS logic design, transistor-level circuit analysis, static timing, power estimation, and layout rules. The three sets progress from basic MOSFET operation through multi-stage design to GATE-level timing and power problems.
Difficulty levels
BeginnerIntermediateAdvanced
Practice sets
Beginner: Definitions and Direct Formulas
BeginnerState the condition for a MOSFET to operate in the saturation region and write the drain current expression.
Answer: An NMOS transistor is in saturation when V_GS > V_th and V_DS >= V_GS - V_th. The drain current is: I_D = (μ_n C_ox W/2L)(V_GS - V_th)^2 (ignoring channel length modulation).
Saturation occurs when the channel is pinched off at the drain end. The condition V_DS >= V_GS - V_th ensures pinch-off. In the saturation region, I_D depends on V_GS but is (ideally) independent of V_DS. Channel length modulation introduces a weak V_DS dependence: I_D = (μ_n C_ox W/2L)(V_GS - V_th)^2 (1 + λ V_DS).
What is the switching threshold voltage V_M of a CMOS inverter?
Answer: V_M is the input voltage at which V_out = V_in. For a symmetrical inverter where the PMOS and NMOS are sized so that they have equal drive strengths (k_n = k_p), V_M = V_DD / 2.
At V_in = V_M, both transistors are in saturation simultaneously and the DC gain is maximum. For a symmetric inverter with matched transistors (k_n = k_p), V_M = V_DD / 2. If the NMOS is stronger (k_n > k_p), V_M shifts below V_DD/2. If the PMOS is stronger, V_M shifts above V_DD/2.
Define propagation delay t_p and state how it relates to t_pHL and t_pLH.
Answer: Propagation delay t_p is the average time for the output to respond to an input transition: t_p = (t_pHL + t_pLH) / 2. t_pHL is the delay from 50% input rising to 50% output falling. t_pLH is the delay from 50% input falling to 50% output rising.
t_pHL is dominated by the NMOS pull-down network drive strength. t_pLH is dominated by the PMOS pull-up network. For a symmetrical inverter they are equal. In NAND gates, the series NMOS stack increases t_pHL because the effective on-resistance doubles for 2-input NAND with equal sizing.
Write the expression for dynamic power dissipation in CMOS logic.
Answer: P_dynamic = α C_L V_DD^2 f, where α is the activity factor (probability of a power-consuming transition per clock cycle), C_L is the load capacitance, V_DD is the supply voltage, and f is the clock frequency.
Energy α C_L V_DD^2 is drawn from the supply on every low-to-high output transition and dissipated in the PMOS and subsequently in the NMOS on the high-to-low transition. Since this happens α f times per second, power is α C_L V_DD^2 f. V_DD has the strongest effect because power scales as V_DD^2.
Intermediate: Multi-step Problems
IntermediateSize the PMOS transistor in a CMOS NAND2 gate so that it has the same drive strength as a reference NMOS of width W_n. Given: μ_n = 2 μ_p.
Answer: For the NAND2 pull-down path, two NMOS transistors are in series. Each NMOS has effective resistance R_n = 1/(μ_n C_ox (W_n/L)). Series resistance = 2 R_n. To match this with the PMOS (single transistor in pull-up), set R_p = 2 R_n. Since R_p = 1/(μ_p C_ox (W_p/L)) and μ_n = 2 μ_p, we get W_p = 2 × 2 × W_n = 4 W_n.
The NAND2 pull-down has two series NMOS, doubling the pull-down resistance compared to an inverter. The PMOS pull-up consists of two parallel transistors, halving the pull-up resistance per transistor. To equalise t_pHL and t_pLH, the total pull-up resistance must equal the total pull-down resistance. R_pmos_total = R_p/2 (parallel). Setting R_p/2 = 2 R_n gives R_p = 4 R_n. Using R proportional to 1/(μW): W_p/(μ_p) = 4 W_n/(μ_n) => W_p = 4 μ_p W_n / μ_n = 4 × (1/2) × W_n = 2 W_n per PMOS transistor.
A combinational path has three stages with delays 200 ps, 350 ps, and 150 ps. Setup time is 80 ps, hold time is 30 ps, and clock-to-Q delay is 120 ps. Find the minimum clock period and maximum operating frequency.
Answer: T_min = t_cq + t_logic + t_setup = 120 + (200 + 350 + 150) + 80 = 120 + 700 + 80 = 900 ps. f_max = 1 / T_min = 1 / (900 × 10^-12) ≈ 1.11 GHz.
The critical path constraint is T >= t_cq + t_pd_max + t_setup. Sum the three logic stage delays: 200 + 350 + 150 = 700 ps. Add clock-to-Q (120 ps) and setup time (80 ps) to get T_min = 900 ps. The hold time constraint is t_cq + t_pd_min >= t_hold; hold time violations are independent of clock frequency and must be fixed with buffer insertion, not by changing the clock period.
Estimate the total power dissipated by a CMOS chip with C_L = 20 pF per gate, 10^6 gates, α = 0.1, V_DD = 1.2 V, f = 500 MHz. Also estimate leakage if average subthreshold current per gate is 10 nA.
Answer: P_dynamic = α C_L V_DD^2 f N = 0.1 × 20 × 10^-12 × 1.44 × 500 × 10^6 × 10^6 = 1.44 W. P_leakage = I_leak × V_DD × N = 10 × 10^-9 × 1.2 × 10^6 = 12 mW.
Dynamic power: 0.1 × 20e-12 × 1.44 × 5e8 × 1e6 = 0.1 × 20 × 1.44 × 500 × 10^(-12+6+6) W. Work step by step: 0.1 × 20 = 2, × 1.44 = 2.88, × 500 = 1440, × 10^0 = 1440 mW = 1.44 W. Leakage: 10 nA/gate × 1.2 V × 10^6 = 12 mW, which is about 1% of dynamic power at this frequency but becomes dominant at lower activity factors.
Advanced: GATE-style Questions
AdvancedAn NMOS transistor has W/L = 10, μ_n C_ox = 100 μA/V^2, V_th = 0.5 V, λ = 0.1 V^-1. With V_GS = 1.5 V and V_DS = 2 V, find I_D. Then find V_DS at the boundary between triode and saturation.
Answer: V_GS - V_th = 1.0 V. V_DS = 2 V >= 1.0 V, so the transistor is in saturation. I_D = (μ_n C_ox W/2L)(V_GS - V_th)^2 (1 + λ V_DS) = (100e-6 × 10/2)(1.0)^2 (1 + 0.1 × 2) = 500 μA × 1.2 = 600 μA. Boundary: V_DS_sat = V_GS - V_th = 1.0 V.
The trap is to forget the channel length modulation factor (1 + λ V_DS). Without it, I_D = 500 μA. With λ = 0.1 V^-1 and V_DS = 2 V, the correction factor is 1.2, giving 600 μA. The boundary between triode and saturation is always V_DS = V_GS - V_th, regardless of channel length modulation.
A CMOS inverter has V_DD = 1.8 V, switching threshold V_M = 0.9 V, V_thn = 0.4 V, V_thp = -0.4 V, μ_n C_ox = 120 μA/V^2, μ_p C_ox = 60 μA/V^2, L = 0.18 μm. Find the required W_p if W_n = 0.36 μm.
Answer: At V_M = V_DD/2, by symmetry k_n = k_p. k_n = μ_n C_ox W_n/L = 120 × 0.36/0.18 = 240 μA/V^2. Setting k_p = 240: μ_p C_ox W_p/L = 240 => W_p = 240 × 0.18 / 60 = 0.72 μm.
The trap is to assume W_p = W_n because the threshold voltages are symmetric. The mobility difference (μ_n = 2μ_p) means the PMOS must be twice as wide as the NMOS to achieve equal drive strength and a symmetric switching threshold at V_DD/2. Confirm: k_p = 60 × 0.72/0.18 = 240 μA/V^2 = k_n. The switching threshold formula for general sizing is V_M = (V_thn + sqrt(k_p/k_n)(V_DD + V_thp)) / (1 + sqrt(k_p/k_n)).
Lab exercises
- Simulate a CMOS inverter DC transfer characteristic in LTspice, extract V_M and noise margins: lab-cmos-inverter-spice
- Design and simulate a 4-bit ripple carry adder at transistor level, measure critical path delay: lab-ripple-adder-vlsi
- Perform static timing analysis on a 3-stage pipeline using a timing spreadsheet, identify setup and hold violations: lab-sta-pipeline
Revision checklist
- Can you draw the CMOS NAND2 and NOR2 transistor-level schematics from memory and label all sources, drains, and gates?
- Can you derive the sizing rule for NMOS series stacks in complex gates without consulting notes?
- Can you calculate t_pHL for a CMOS inverter given transistor parameters and a load capacitance?
- Can you identify whether a MOSFET is in cutoff, triode, or saturation given V_GS, V_DS, and V_th?
- Can you apply the setup time constraint equation and compute f_max for a pipelined circuit?
- Can you break down total CMOS power into dynamic, short-circuit, and leakage components and state which dominates at low frequency?