Delays in Dataflow

In Verilog dataflow modeling, timing is controlled through delay specifications attached to continuous assignments. Understanding how delays work is essential for accurately modeling real gate and wire behavior in digital circuits, and is a frequently tested topic in university practicals and GATE-level digital design questions.

Core Concept: What Are Dataflow Delays

In Verilog, a continuous assignment using the assign keyword models combinational logic. A delay can be added to this assignment using the #delay notation. When a delay is specified, the right-hand side (RHS) expression is evaluated immediately when any input changes, but the result is scheduled to update the left-hand side (LHS) output only after the specified delay time units.

There are two conceptual types of delays important to understand: inertial delay and transport delay. These two models differ in how they handle pulses shorter than the delay value. In practical Verilog usage, the assign #N syntax implements inertial-like behavior by default because if the input changes again before the delay expires, the scheduled event is cancelled and replaced by the new one.

Inertial Delay

Inertial delay is the default model used in gate-level and dataflow Verilog. It reflects the physical behavior of real logic gates, which cannot respond to pulses narrower than their propagation delay. If an input toggles at time T and toggles back before T + delay, the output never changes because the first scheduled event is cancelled by the second event. This naturally filters out glitches and very short spikes on signals.

In Verilog, writing assign #10 out = a | b; means that whenever a or b changes, the simulator evaluates a | b immediately but schedules the result to appear on out after 10 time units. If a changes again before 10 units pass, the pending update is replaced by a new evaluation.

Transport Delay

Transport delay models a wire or transmission line where every transition, no matter how short, eventually reaches the output after a fixed propagation delay. Unlike inertial delay, transport delay does not filter pulses. A pulse of width 1 ns will appear at the output shifted by the delay, regardless of how long the delay is. This model is more relevant for interconnect simulation and is not directly available via assign syntax in standard Verilog; it is implemented in behavioral blocks or specialized constructs in some simulators.

Mathematical Expression

For a continuous assignment with delay d, the output update rule under inertial delay is: if input changes at time T1 and again at T2, the output changes only if T2 - T1 >= d. For transport delay, output always changes at T1 + d regardless of subsequent input changes. In simulation time units, the assign statement assign #d out = expr; schedules an event at current_time + d whenever the expression evaluates to a new value.

Practical Understanding

Delays in dataflow modeling are critical when you need to simulate timing behavior of combinational circuits. Without delays, all logic evaluates in zero simulation time (delta cycles), which is fine for functional verification but does not reflect real hardware timing. Adding proper delays to assign statements allows you to verify setup and hold time violations, glitch behavior, and propagation timing through logic paths.

In ASIC and FPGA design, post-synthesis and post-layout netlists use gate-level delays derived from the technology library. During simulation of these netlists, inertial delays correctly model real gate behavior including glitch suppression, which is an important accuracy concern in timing verification flows.

Given:
Assign statement: assign #8 z = a ^ b;
Input a changes to 1 at time 5ns, then back to 0 at time 10ns.
Delay d = 8ns.

Why this formula applies:
Inertial delay: output changes only if input stays changed for at least d time units.
Pulse width = 10 - 5 = 5ns, which is less than d = 8ns.

Formula:
Output changes only if pulse_width >= d

Substitution:
pulse_width = 5ns, d = 8ns
5 < 8

Calculation:
Condition not met, scheduled update at time 5+8=13ns is cancelled at time 10ns.

Final Answer:
z does NOT change. The pulse is filtered out by inertial delay.

Exam Tip: In Verilog assign #N, if input toggles twice within N time units, the output does NOT change at all. This is inertial delay filtering. A common trap is assuming the output changes twice with a delay shift.

Quick Revision

• assign #d out = expr; schedules LHS update d time units after RHS changes.
• Inertial delay: cancels pending update if input changes again before delay expires. Filters short pulses.
• Transport delay: propagates all transitions regardless of width, shifted by d. Not natively in assign syntax.
• Default Verilog assign delay is inertial in behavior due to event rescheduling.
• Pulse width < delay: output unchanged (inertial). Pulse width >= delay: output changes after d.
• Delays do not affect functional simulation correctness but are essential for timing verification.
• Exam trap: Do not confuse delay on assign with delay inside always blocks, which work differently.