gate delays

Gate delays in Verilog allow simulation to model the realistic timing behavior of logic gates, including how quickly outputs respond to input changes. Understanding rise, fall, and turn-off delays, as well as the min/typ/max delay specification system, is critical for timing-accurate simulation and is a regularly tested concept in digital design coursework and competitive examinations.

Core Concept: Why Gate Delays Exist

In real digital hardware, logic gates do not switch instantaneously. There is a finite time between when an input changes and when the output responds. This is called propagation delayand it arises from the physical capacitance of transistors, interconnect resistance, and the current drive capability of the gate output. Verilog models this through gate delay specifications attached to primitive instantiations.

Without specifying delays, all Verilog gate primitives operate in zero simulation time (or delta time), which is useful for functional simulation but does not reflect realistic timing. By adding delay values, the simulator accurately reflects when output transitions actually occur relative to input changes, enabling timing verification without needing a full SPICE-level simulation.

Rise Delay, Fall Delay, and Turn-off Delay

Three distinct delays can be associated with a gate output. Rise delay (tr) is the time from when the output is supposed to change from 0 to 1, measured from the triggering input change. Fall delay (tf) is the time for output to transition from 1 to 0. Turn-off delay (tto) applies only to tristate gates such as bufif1 and represents the time for the output to move from a driven state (0 or 1) to the high-impedance state Z.

The specification formats are: single delay #d applies the same value to all transitions. Two-value #(tr, tf) specifies rise and fall separately. Three-value #(tr, tf, tto) specifies all three. For example: and #(4, 6) g1(y, a, b); means rise delay = 4, fall delay = 6. This level of control is important because most real gates have asymmetric rise and fall delays due to NMOS/PMOS transistor sizing differences.

Min/Typ/Max Delay Specification

Real silicon fabrication introduces variation: a gate might be slower at low temperature with slow-corner process, typical at nominal, and faster at high temperature fast-corner. Verilog supports min:typ:max delay notation to capture this spread. The format is: #(min:typ:max) for a single transition, or #(tr_min:tr_typ:tr_max, tf_min:tf_typ:tf_max) for separate rise and fall. The simulator uses one of the three values depending on which simulation corner is selected at runtime.

For example: and #(2:3:5, 1:2:4) g1(y, a, b); specifies rise min=2, typ=3, max=5 and fall min=1, typ=2, max=4. Running with +maxdelays switch uses max values, +mindelays uses min values, and +typdelays uses typical values. This is directly relevant to worst-case timing analysis during chip sign-off.

Mathematical Expression

For a gate with rise delay tr and fall delay tf, the output event timing is: if input changes at time T causing a 0-to-1 transition, output updates at T + tr. If input causes a 1-to-0 transition, output updates at T + tf. For a path through N gates with individual delays, total rise path delay = sum of all rise delays encountered, total fall path delay = sum of all fall delays on that path. The critical path delay is the maximum among all paths from input to output.

Given:
A circuit: input a → and gate → or gate → output y.
AND gate: #(3:4:6, 2:3:5) — rise min:typ:max = 3:4:6, fall = 2:3:5
OR gate: #(2:3:4, 1:2:3) — rise = 2:3:4, fall = 1:2:3
Simulation run with +maxdelays.

Why this formula applies:
Max corner timing analysis uses maximum delay values for each transition.
Critical path for rising output = sum of max rise delays.

Formula:
Total_rise_max = and_rise_max + or_rise_max
Total_fall_max = and_fall_max + or_fall_max

Substitution:
Total_rise_max = 6 + 4 = 10 time units
Total_fall_max = 5 + 3 = 8 time units

Calculation:
Worst case rise delay = 10 time units
Worst case fall delay = 8 time units

Final Answer:
Maximum propagation delay (worst case) = 10 time units for rising output.

Exam Tip: When a single delay value #d is given to a gate, it applies equally to rise, fall, and turn-off. When two values #(tr, tf) are given, turn-off delay equals the smaller of tr and tf by default in most simulators.

Mechanism: How the Simulator Handles Gate Delays

• When an input changes, the simulator evaluates the gate output and schedules the result to appear after the appropriate rise or fall delay.
• If a second input change arrives before the scheduled event fires, the simulator cancels the pending event and reschedules based on the new result (inertial behavior).
• Min/typ/max values allow the same model to be used for timing sign-off across different process corners without changing the netlist.
• Turn-off delay is only meaningful for tristate drivers; for standard logic gates it is not applicable.
• In most physical timing flows, delays in the netlist are back-annotated from STA tools using an SDF (Standard Delay Format) file rather than being hardcoded in the Verilog instantiation.

Quick Revision

• Rise delay: output 0-to-1 transition delay. Fall delay: output 1-to-0 transition delay. Turn-off delay: output to high-Z delay (tristate only).
• Single delay: #d applies to all transitions. Two-value: #(tr, tf). Three-value: #(tr, tf, tto).
• Min:Typ:Max format: #(2:4:6) — selected by +mindelays, +typdelays, or +maxdelays simulator flags.
• Critical path delay = sum of rise (or fall) delays along the longest logic path from input to output.
• Max corner used for setup time (slow scenario). Min corner used for hold time (fast scenario).
• SDF back-annotation overrides Verilog delay values in real chip timing simulations.
• Exam trap: When only #(tr, tf) given, turn-off delay is NOT zero — it defaults to min(tr, tf) in many simulators. Read simulator documentation carefully.