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Contents

Basics

Introduction to HDLs Verilog Module Structure Data Types and Logic Values Vectors and Arrays Lexical Conventions Verilog Operators Port Connection Rules

Behavioral Modeling

Procedural Blocks Blocking vs Non-Blocking Control Statements Loops in Verilog FSM Behavioral Modeling Timing Controls Block Statements Task and Function

Dataflow Modeling

Continuous Assignment Delays in Dataflow Conditional Operator Modeling Combinational Logic

Structural Modeling

Gate Level Modeling gate delays Module Instantiation Switch Level Modeling User Defined Primitives Generate Blocks

Sequential Circuits

Modeling Flip-Flops Modeling Latches Modeling Counters Modeling Shift Registers Synchronous Memories

Combinational Circuits

Modeling Multiplexers Modeling Decoders/Encoders Modeling ALUs Modeling Adders Modeling Comparators

Verification

Testbench Basics System Tasks Simulation Time Randomization Assertions Verification Plan

Other Topics

FPGA vs ASIC Synthesis Concepts Verilog 2001 Features PLI Basics

Other Subjects

Analog Electronics Digital Electronics Signals & Systems Control Systems Electromagnetic Theory Digital Communication Analog Communication Network Analysis Microprocessors VLSI Design Power Electronics Embedded Systems DSP Electronic Devices

Section Progress17%

1 of 6 articles

Gate Level Modeling

Built-in primitives (and, or, not), gate delays.

Updated: 19 March 2026

7 min read

Gate Level Structural Modeling

Test your knowledge on this topic.

Question 1 of 3

Q1.In a Verilog primitive instantiation like nand(out, in1, in2);, what is the strict port connection rule?

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Switch Level Modeling

NMOS, PMOS, CMOS switches, transmission gates.

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User Defined Primitives

Creating custom combinational/sequential primitives.

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Generate Blocks

Conditional and loop generate for scalable structures.

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Modeling Latches

Level sensitive behavior, inferring latches accident.

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Module Instantiation

Port mapping by order, by name.

6 min read

Modeling Combinational Logic