Gate Level Modeling

Gate-level modeling in Verilog allows designers to build circuits by directly instantiating logic gate primitives provided by the language. This style of modeling closely mirrors the actual hardware netlist and is important for understanding how synthesis output looks, as well as for accurately simulating gate delay behavior at the lowest level of abstraction.

Core Concept: Built-in Gate Primitives

Verilog provides a set of built-in gate primitives that can be instantiated directly without any module definition. These include: and, or, not, nand, nor, xor, xnor, and buf. There are also tristate variants: bufif0, bufif1, notif0, and notif1. These primitives represent real combinational hardware elements and are the building blocks of any digital circuit at the netlist level.

The general instantiation syntax is: primitive_type [instance_name] (output_port, input1, input2, ...);. The first port is always the output for most gate primitives. The instance name is optional but recommended for clarity during debugging. Multiple instances of the same primitive can be created with different names.

Port Order Rules for Primitives

For and, or, nand, nor, xor, and xnor gates: the first port is the single output, followed by two or more inputs. For not and buf gates: only one input is allowed. For tristate gates like bufif1: the port order is (output, input, control). Getting the port order wrong is one of the most common mistakes in gate-level modeling.

Gate Delays in Primitives

A gate delay can be specified during primitive instantiation using the #delay notation placed after the primitive name: and #5 g1(y, a, b);. This specifies a propagation delay of 5 time units from any input change to the output update. More detailed delay specifications can provide separate values for rise delay, fall delay, and turn-off delay using the format #(rise, fall) or #(rise, fall, turnoff).

Building a Circuit Using Gate Primitives

A complete combinational circuit is built by instantiating multiple primitives and connecting them through intermediate wire signals. For example, a two-level AND-OR circuit implementing F = AB + CD uses: two AND gates producing intermediate signals, followed by one OR gate combining them. Internal connections use wire declarations. This style directly represents the circuit netlist and corresponds exactly to what synthesis tools produce after logic optimization.

Mathematical Expression

Each gate primitive implements one Boolean operator exactly. For a chain of N gates in series, the total propagation delay is the sum of individual gate delays: T_total = d1 + d2 + ... + dN. For parallel paths, the longest path (critical path) determines the maximum propagation delay. This analysis directly maps to static timing analysis (STA) performed during ASIC sign-off.

Given:
Build a full adder sum bit using gate-level primitives.
Inputs: a, b, cin. Sum = a XOR b XOR cin.
Gate delay of each XOR gate = 3ns.

Why this formula applies:
Sum of full adder = a ^ b ^ cin = two cascaded XOR gates.
Critical path delay = sum of delays along input to output.

Formula:
wire w1;
xor #3 x1(w1, a, b);
xor #3 x2(sum, w1, cin);
Total delay = delay_x1 + delay_x2

Substitution:
Total delay = 3 + 3

Calculation:
Total propagation delay = 6ns

Final Answer:
sum signal is valid 6ns after a, b, or cin changes.

Exam Tip: In Verilog gate primitives, the FIRST port is always the OUTPUT for standard gates (and, or, nand, nor, xor, buf, not). For tristate gates (bufif1), order is (output, input, control). Getting this wrong gives wrong simulation silently.

How Gate-Level Instantiation Works

• Each gate primitive instantiation creates one logic element in the netlist with defined input-output connections.
• Internal signals between gates are declared as wire type and carry no state information.
• Gate delays specified with #N control when output changes relative to input changes in simulation.
• The first port in the primitive port list is always the output for standard gates — this is a fixed rule with no exceptions.
• Multiple input gates (and, or) can have more than two input ports: and g1(y, a, b, c); produces a 3-input AND.

Quick Revision

• Built-in primitives: and, or, not, nand, nor, xor, xnor, buf, bufif0, bufif1, notif0, notif1.
• Port order: (output, input1, input2, ...) for standard gates. NOT gate: (output, input) only.
• Instance name is optional: and (y, a, b); is valid but and g1(y, a, b); is preferred.
• Gate delay syntax: and #5 g1(y, a, b); — 5 time units of propagation delay.
• Multi-input gates: and, or, nand, nor, xor, xnor accept two or more inputs.
• Gate-level models match post-synthesis netlists — important for timing simulation.
• Exam trap: Mixing up port order (putting input first) produces wrong output silently in simulation.