Loops in Verilog

Loops in Verilog provide a way to describe repetitive operations concisely within procedural blocks. They are widely used in testbenches to generate stimulus, in RTL for generating repeated hardware structures, and in parameterized designs where the number of iterations is determined at elaboration time. Understanding when and how each loop type applies is important for both simulation and synthesis.

Core Concept: Why Loops Exist in Verilog

Hardware is inherently parallel and repetitive. An 8-bit ripple carry adder consists of 8 identical full adder cells. A shift register consists of N identical flip-flops connected in a chain. Writing these structures out manually statement by statement is both error-prone and inflexible. Verilog loops allow designers to describe such regular structures compactly, with a loop variable indexing each element.

In the context of simulation, loops also enable testbenches to generate repetitive stimulus without writing each pattern manually. A for loop can iterate over all 256 input combinations of an 8-bit input, applying each one and checking the output automatically. Without loops, such exhaustive testing would require enormous repetitive code.

The for Loop

The for loop in Verilog follows the same structure as in C: an initialization, a condition, and an increment expression. It is the most commonly used loop in synthesizable Verilog. When the loop bounds and increment are constants known at compile time, synthesis tools unroll the loop, replacing it with N copies of the loop body, each parameterized by the loop index. The resulting hardware is fully combinational or sequential depending on the context.

For a for loop to be synthesizable, the loop must terminate after a fixed, statically determinable number of iterations. If the loop bound depends on a runtime variable, the tool cannot determine how many hardware copies to generate, and the loop is not synthesizable. The loop variable itself must be declared as integer or a sized reg type.

The while Loop

The while loop evaluates a condition at the start of each iteration and continues as long as the condition is true. If the initial condition is false, the body never executes. In simulation, while loops are useful when the number of iterations is determined by dynamic signal values. In synthesis, a while loop can be synthesized only if the tool can statically determine that it will always terminate in a fixed number of iterations, which is rarely guaranteed in practice. It is primarily a simulation construct.

The repeat Loop

The repeat loop executes its body a fixed number of times specified by a constant expression. The count is evaluated once when the loop begins and does not change during execution. It is concise and clear when a specific number of repetitions is needed, such as applying a burst of 10 clock cycles in a testbench or repeating a shift operation a fixed number of times. Like while, it is generally used in simulation rather than synthesis unless the count is a compile-time constant.

The forever Loop

The forever loop runs infinitely. It has no termination condition and never exits on its own. It must always contain a timing control statement inside its body, such as a delay or an event trigger, otherwise the simulator enters an infinite zero-time loop and hangs. The most common use of forever is clock generation in testbenches, where the clock toggles at a fixed period indefinitely. forever is not synthesizable.

Given:
Compute 8-bit bitwise AND reduction (AND all bits of a vector together) using a for loop.
Input: data[7:0], Output: result (1-bit)

Why this formula applies:
Repetitive AND operation across N bits is naturally expressed as a for loop.
Loop bounds are constant (0 to 7), so synthesis can unroll it.

Formula:
result = data[0] & data[1] & ... & data[7]
Implemented with for loop:
  result = 1'b1;
  for (i = 0; i < 8; i = i + 1)
    result = result & data[i];

Substitution:
data = 8'b1111_1110 (bit 0 is 0)

Calculation:
i=0: result = 1 & 0 = 0
i=1 to i=7: result = 0 & 1 = 0 (stays 0)

Final Answer with units:
result = 1'b0
The AND reduction correctly returns 0 because bit[0] is 0.
If all bits were 1, result would be 1.

Exam Tip: In GATE and university exams, for loops with constant bounds are synthesizable; while and forever loops are simulation-only unless bounds are provably static. A forever loop without a timing control statement inside it causes the simulator to hang at time zero. This is a common trap in simulation-focused questions.

Mechanism: How a for Loop Is Unrolled to Hardware

• for loop with constant bounds: synthesizable, tool unrolls into N copies of the loop body in hardware.
• while loop: synthesizable only if termination is provably static; primarily a simulation construct.
• repeat loop: executes a fixed N times, N evaluated at loop start; mainly used in testbenches.
• forever loop: runs indefinitely, must have timing control inside to avoid zero-time infinite loop; not synthesizable.
• In simulation, all four loop types are valid; in synthesis, only for with constant bounds is reliably supported.
• The loop variable in a for loop must be declared as integer or reg and must not drive hardware outputs directly.

Quick Revision

• for loop: init; condition; increment. Synthesizable if bounds are compile-time constants.
• while loop: condition checked before each iteration. Use in testbenches; not reliably synthesizable.
• repeat (N): runs body exactly N times. Mostly simulation use for clock and stimulus generation.
• forever: infinite loop. Must have # delay or @event inside. Used for clock generation in testbenches. Not synthesizable.
• Synthesis unrolls for loops: each iteration becomes a separate hardware instance in the netlist.
• for loop variable must be integer type; it has no direct hardware equivalent after synthesis.
• Exam trap: a forever loop without timing control inside it hangs the simulator at time zero permanently.