⌘K

Contents

Basics

Introduction to HDLs Verilog Module Structure Data Types and Logic Values Vectors and Arrays Lexical Conventions Verilog Operators Port Connection Rules

Behavioral Modeling

Procedural Blocks Blocking vs Non-Blocking Control Statements Loops in Verilog FSM Behavioral Modeling Timing Controls Block Statements Task and Function

Dataflow Modeling

Continuous Assignment Delays in Dataflow Conditional Operator Modeling Combinational Logic

Structural Modeling

Gate Level Modeling gate delays Module Instantiation Switch Level Modeling User Defined Primitives Generate Blocks

Sequential Circuits

Modeling Flip-Flops Modeling Latches Modeling Counters Modeling Shift Registers Synchronous Memories

Combinational Circuits

Modeling Multiplexers Modeling Decoders/Encoders Modeling ALUs Modeling Adders Modeling Comparators

Verification

Testbench Basics System Tasks Simulation Time Randomization Assertions Verification Plan

Other Topics

FPGA vs ASIC Synthesis Concepts Verilog 2001 Features PLI Basics

Other Subjects

Analog Electronics Digital Electronics Signals & Systems Control Systems Electromagnetic Theory Digital Communication Analog Communication Network Analysis Microprocessors VLSI Design Power Electronics Embedded Systems DSP Electronic Devices

Section Progress50%

4 of 8 articles

Loops in Verilog

For, while, repeat, forever loops.

Updated: 19 March 2026

8 min read

Verilog Loop Constructs

Test your knowledge on this topic.

Question 1 of 3

Q1.How does a synthesis tool interpret a for loop containing combinational logic?

Related Articles

Task and Function

Subroutines, differences, automatic re-entrancy.

5 min read

Block Statements

Begin-end, fork-join parallel blocks.

9 min read

Timing Controls

Delay control #, event control @, wait statement.

4 min read

Procedural Blocks

Always block, initial block, sensitivity lists.

4 min read

Blocking vs Non-Blocking

Operators = vs <=, scheduling semantics.

7 min read

Control Statements

FSM Behavioral Modeling