Modeling Shift Registers

Shift registers are fundamental sequential building blocks used in serial communication, data buffering, pipeline stages, and signal delay chains. In Verilog, modeling a shift register requires understanding how data moves bit-by-bit or word-by-word between flip-flops on each clock edge, and how the four configurations — SISO, SIPO, PISO, PIPO — differ in their input and output interfaces.

Core Concept: Shifting Data in Flip-Flop Chains

A shift register is a chain of flip-flops where the output of one stage connects to the input of the next. On every rising clock edge, data moves one position along the chain. The direction of shift (left or right) depends on how the chain is connected in Verilog. The key to modeling all four types lies in understanding how Verilog's concatenation operator {a, b} enables compact shifting expressions.

A 4-bit right-shift SISO register is written as sr <= {si, sr[3:1]}; where si is the serial input. This concatenates the new serial bit at the MSB and drops the LSB, effectively shifting all bits right by one position. After 4 clock cycles, the entire 4-bit input sequence has propagated through all stages. For a left-shift, the expression becomes sr <= {sr[2:0], si};.

SIPO, PISO, and PIPO Configurations

The SIPO (Serial-In Parallel-Out) configuration uses the same shift logic as SISO, but all bits of the register are available simultaneously as parallel outputs. No additional logic is needed beyond exposing the entire register as output. This is used in serial-to-parallel converters in SPI and UART receivers.

The PISO (Parallel-In Serial-Out) configuration requires a load signal. When load is high, all bits of a parallel data bus are loaded into the shift register simultaneously using a blocking or non-blocking parallel assignment. When load is low, the register shifts on each clock, outputting one bit per cycle from the MSB or LSB. This is the basis of SPI transmitters and parallel-to-serial converters.

The PIPO (Parallel-In Parallel-Out) configuration is essentially a parallel register with no shifting. All bits are loaded in parallel and read in parallel. This is the building block of pipeline registers, where a data word is captured and held for one clock cycle before being forwarded. In Verilog, this is simply reg [N-1:0] q; always @(posedge clk) q <= d;.

Mathematical Expression

For a shift register of width N, the latency — the number of clock cycles required for serial data to traverse the entire register — equals N. For PISO, the time to serialize a parallel word of width N is N clock cycles. For SIPO, N clock cycles are needed to receive a full parallel word. The throughput of a serial link using an N-bit PISO/SIPO pair is: f_data = f_clk / N bits per clock, or equivalently the bit rate = f_clk.

Practical Understanding

Shift registers are the foundation of serial communication interfaces. SPI uses a PISO transmitter and a SIPO receiver to move one byte over a single data line in 8 clock cycles. I2C uses a similar principle. In FPGA design, shift registers are often implemented using dedicated shift register primitives (such as SRL16 in Xilinx) that are more area-efficient than chaining individual flip-flops for long delays.

Given:
SIPO shift register, N = 8 bits, serial data = 10110101 (MSB first)
Clock cycles available: 8

Why this formula applies:
SIPO loads 1 bit per cycle; after N cycles, parallel output holds complete word

Formula:
sr <= {si, sr[N-1:1]}  (right shift, si enters at MSB)
Latency = N clock cycles

Substitution:
Cycle 1: si=1, sr=1xxxxxxx
Cycle 2: si=0, sr=10xxxxxx
Cycle 3: si=1, sr=101xxxxx
Cycle 4: si=1, sr=1011xxxx
Cycle 5: si=0, sr=10110xxx
Cycle 6: si=1, sr=101101xx
Cycle 7: si=0, sr=1011010x
Cycle 8: si=1, sr=10110101

Final Answer:
After 8 clock cycles, parallel output = 10110101 = 0xB5

Exam Tip: For a PISO register, the number of clock cycles to output N bits serially equals N. For SIPO, N cycles to assemble the parallel word. GATE questions often ask for latency or minimum clock cycles — always answer N for an N-bit shift register.

Shift Register Data Flow Mechanism

• SISO: sr <= {si, sr[N-1:1]} shifts data right; serial in, serial out after N cycles.
• SIPO: same shift logic; all N bits of register exposed as parallel output simultaneously.
• PISO: load signal controls whether parallel data is loaded or register is shifted out serially.
• PIPO: no shifting; parallel load into register, direct parallel output; used in pipeline registers.
• Latency for serial data traversal = N clock cycles for an N-bit register.

Quick Revision

• SISO: serial in, serial out; shift expression sr <= {si, sr[N-1:1]}.
• SIPO: serial in, all bits available as parallel out; same shift, full register as output.
• PISO: parallel load when load=1; serial shift when load=0; SO = sr[MSB].
• PIPO: parallel load and parallel output; simple register assignment, no shifting.
• Latency = N clock cycles for an N-bit shift register.
• Concatenation {si, sr[N-1:1]} is the core Verilog shift idiom — memorize this.
• Exam trap: confusing left-shift {sr[N-2:0], si} with right-shift {si, sr[N-1:1]}.