Synthesis Concepts

Synthesis is the automated process that transforms a behavioral or structural RTL description written in Verilog or VHDL into a gate-level netlist. It is the bridge between the abstract hardware description a designer writes and the actual logic gates that will be physically implemented in silicon or on an FPGA. Without synthesis, a Verilog file is just a simulation model.

What Synthesis Actually Does

The synthesis tool reads RTL code and creates an internal representation of the design intent. This process starts with elaboration, where the tool parses the Verilog source, resolves module hierarchy, evaluates parameters, and generates statements, and unrolls loops. The result is a flattened or hierarchical representation of all modules.

After elaboration, the tool performs generic synthesis, converting RTL constructs into technology-independent boolean logic. An if-else statement becomes a multiplexer, a case statement becomes a priority encoder or decoder, an always block sensitive to clock becomes a flip-flop with combinational logic feeding its data input. This stage is purely logical and does not yet consider which physical gates will be used.

The final major step is technology mapping, where the technology-independent logic is mapped to actual cells from a standard cell library (for ASIC) or to LUTs and flip-flops (for FPGA). The tool selects cells that minimize the design objective, whether that is timing, area, or power, according to the provided constraints.

RTL Constructs and Their Synthesized Equivalents

Understanding how each Verilog construct synthesizes is critical for writing correct synthesizable RTL. An always @(posedge clk) block infers a set of flip-flops. Every variable assigned inside it and driven by the clock edge becomes a registered output. The combinational logic that computes the next state of those registers is placed between the flip-flop outputs and inputs, forming a typical register-stage pipeline structure.

A combinational always block using always @(*) infers pure combinational logic. If a signal is not assigned in all branches of an if-else or case construct, the synthesis tool will infer a latch to hold the previous value, which is almost always unintentional. This is one of the most common synthesis bugs. Writing complete case statements with a default clause and complete if-else trees avoids unintended latch inference.

The assign statement synthesizes directly to combinational wires or logic gates. Operators such as plus, minus, and multiply map to adders, subtractors, and multiplier arrays in the netlist. A 32-bit multiply can generate a very large sub-circuit and should be used carefully in critical paths.

Timing Constraints and SDC

Synthesis is driven by timing constraints specified in Synopsys Design Constraints (SDC) format. The primary constraint is the clock period, specified with the create_clock command. The synthesis tool calculates the critical path which is the longest combinational delay between two flip-flops, and optimizes the logic to ensure this delay fits within the required clock period.

If the critical path delay is 8 ns and the clock period is 10 ns, the design meets timing with 2 ns of slack. Positive slack means timing is satisfied. Negative slack means the design fails timing and the synthesis tool will attempt further optimization, or the engineer must restructure the RTL to shorten the critical path, for example by pipelining.

Optimization Techniques Used During Synthesis

Synthesis tools apply several automated optimization passes. Constant propagation eliminates logic driven by known constant values. If a parameter sets a bus width to 8, all logic beyond 8 bits is removed. Dead code elimination removes logic whose output is never used anywhere in the design. Retiming redistributes flip-flops across combinational logic stages to balance path delays and improve the maximum clock frequency without changing functional behavior.

Resource sharing reduces area by using a single adder for two additions that can never occur simultaneously, controlled by a multiplexer. This is particularly useful in FSM-based designs where different states perform similar arithmetic on different operands.

Numerical Example: Critical Path and Clock Frequency

The maximum operating frequency of a synthesized design is determined by the critical path delay. If the total combinational delay from one flip-flop output through the combinational logic to the next flip-flop data input is T_comb, and the flip-flop clock-to-Q delay is T_cq and setup time is T_setup, then the minimum clock period is T_clk = T_cq + T_comb + T_setup.

Given:
Flip-flop clock-to-Q delay (T_cq) = 0.3 ns
Combinational logic delay (T_comb) = 5.4 ns
Flip-flop setup time (T_setup) = 0.3 ns

Why this formula applies:
The clock period must accommodate all delays in the register-to-register path.

Formula:
T_clk(min) = T_cq + T_comb + T_setup
F_max = 1 / T_clk(min)

Substitution:
T_clk(min) = 0.3 + 5.4 + 0.3 = 6.0 ns

Calculation:
F_max = 1 / 6.0 ns = 1 / (6 x 10^-9)

Final Answer:
F_max = 166.67 MHz
The design can operate up to 166.67 MHz after synthesis.

Exam Tip: GATE frequently asks about latch inference. If an if statement inside always @(*) does not cover all conditions and has no else, the signal infers a latch. To avoid it, always assign a default value at the start of the always block or use a full else clause. Latches are level-sensitive and violate synchronous design practices.

Common Synthesis Issues

• Unintended latch inference occurs when combinational always blocks have incomplete assignment coverage across all branches.
• Multiple drivers for the same net cause synthesis errors and must be resolved by ensuring only one always block or assign statement drives each wire.
• Use of initial blocks and delay statements such as #10 in RTL are simulation constructs and are ignored or cause errors during synthesis.
• Casex and casez statements synthesize differently depending on the tool. Casex treats X and Z as don't-care. Misuse can lead to incorrect priority logic.
• Arithmetic on signed versus unsigned operands must be controlled explicitly using the signed keyword in Verilog 2001 to avoid incorrect sign extension in synthesized circuits.

Quick Revision

• Synthesis flow: RTL source to elaboration to generic synthesis to technology mapping to gate-level netlist.
• always @(posedge clk) infers flip-flops. always @(*) infers combinational logic.
• Incomplete if-else or case in always @(*) infers latches. Always use default assignments or complete branches.
• Critical path determines maximum clock frequency: F_max = 1 / (T_cq + T_comb + T_setup).
• SDC constraints guide synthesis optimization. Positive slack means timing is met; negative slack means the design fails timing.
• Exam trap: Initial blocks and delay statements are not synthesizable. They are for simulation only.
• Synthesis tools perform constant propagation, dead code elimination, retiming, and resource sharing automatically.