Vectors and Arrays

Real hardware designs rarely operate on single-bit signals. Buses carrying 8, 16, 32, or 64 bits are fundamental to datapaths, memories, and communication interfaces. Verilog provides vectors for multi-bit signals and arrays for collections of storage elements, both of which are essential for writing synthesizable hardware descriptions.

GATE questions on vectors test bit-selection, part-selection, and concatenation operators. Questions on arrays focus on memory declaration and access syntax. Both topics appear regularly in Verilog-based GATE questions and form the backbone of datapath design problems.

Core Concept: Vectors

A vector in Verilog is a multi-bit reg or wire declared with a range specifier. The syntax is reg [7:0] data; which declares an 8-bit wide register named data. The leftmost index in the range is the most significant bit and the rightmost is the least significant bit. This is called big-endian bit ordering and is by far the most common convention. The alternative reg [0:7] data; places bit 0 as the MSB, which is unusual but valid.

Individual bits of a vector can be accessed using bit-select syntax: data[3] reads bit 3. A contiguous range of bits can be accessed using part-select syntax: data[5:2] selects a 4-bit slice from bit 5 down to bit 2. Part-selects are used extensively in datapath operations such as sign extension, byte extraction, and field manipulation.

Core Concept: Arrays

An array in Verilog is a collection of reg or wire elements. The declaration reg [7:0] mem [0:255]; creates 256 storage elements, each 8 bits wide. The first range [7:0] defines the width of each element (the vector part), and the second range [0:255] defines the depth (number of elements). This is how a ROM or RAM is modeled in Verilog. The total storage capacity of this array is 256 x 8 = 2048 bits = 256 bytes.

Array elements are accessed using mem[addr] which returns the full 8-bit word at address addr. To access a specific bit within an array element, use mem[addr][bit] for example mem[5][3] reads bit 3 of the 6th memory word. Note that part-select on an array element (mem[addr][5:2]) is not always supported in older Verilog tools and should be used with caution.

Mathematical Expression: Memory Sizing

For a memory declared as reg [W-1:0] mem [0:D-1]; where W is the word width in bits and D is the depth (number of addresses), the total memory capacity in bits is W x D. The number of address bits required to uniquely address all D locations is ceil(log2(D)). This formula is critical for designing address decoders and memory interface logic.

Solved Numerical Example

A Verilog memory is declared as reg [15:0] rom [0:1023];. Calculate the total storage capacity in kilobits and kilobytes, and determine the minimum number of address bits needed to access all locations.

Given:
Word width (W) = 16 bits  (from [15:0])
Depth (D) = 1024 locations  (from [0:1023])

Why this formula applies:
Total bits = W x D
Address bits = ceil(log2(D))

Formula:
Capacity (bits) = W x D
Address bits = ceil(log2(D))

Substitution:
Capacity = 16 x 1024 = 16384 bits
Address bits = ceil(log2(1024)) = ceil(10) = 10

Calculation:
Capacity in kilobits = 16384 / 1000 = 16.384 kb
Capacity in kilobytes = 16384 / 8 / 1024 = 2 KB
Address bus width = 10 bits (to address 1024 locations)

Final Answer:
Total capacity = 16384 bits = 2 KB. Address bus = 10 bits.

Exam Tip: In GATE, the first range in a 2D array declaration is the vector width (bit dimension) and the second range is the array depth (address dimension). A common trap is reversing these two. Also remember: you cannot use a variable as a part-select index in Verilog-2001 without using indexed part-select (+: or -:) syntax.

Practical Implication

Memory arrays in Verilog are used to model ROM, RAM, register files, and FIFOs. In FPGA designs, tools like Vivado infer Block RAM from array declarations, provided the access pattern matches the BRAM template (synchronous read/write with clock enable). If the array is small enough, the tool may infer distributed RAM or even registers instead. Understanding array sizing directly impacts resource utilization estimates in FPGA implementation.

• Bit-select data[n] extracts a single bit. Part-select data[m:n] extracts a contiguous multi-bit slice. Both can appear on left or right side of an assignment.
• Concatenation operator {} joins multiple signals or constants into a wider vector. Replication {N{expr}} repeats a bit pattern N times.
• Indexed part-select data[base +: width] selects width bits starting from base upward. data[base -: width] selects width bits going downward. The base can be a variable but width must be a constant.
• Memory arrays are declared with two range specifiers. The first specifies word width (vector dimension). The second specifies array depth (address dimension).
• Total memory capacity = word width x depth. Address bus width = ceil(log2(depth)).

Quick Revision

• Vector declaration: reg [MSB:LSB] name; Standard convention is big-endian: reg [7:0] data (bit 7 = MSB).
• Bit-select: data[n] gives single bit. Part-select: data[m:n] gives slice. Both valid on left-hand side of assignment.
• Memory declaration: reg [W-1:0] mem [0:D-1]; where W = word width, D = depth. Total bits = W x D.
• Address bits required = ceil(log2(D)). For D = 1024, address bits = 10.
• Concatenation {} joins vectors. Replication {N{x}} repeats x N times. Both are very common in GATE HDL questions.
• Indexed part-select +: counts up, -: counts down. Width must be a constant. Useful for byte-lane access in loops.
• Key trap: Do not confuse vector width with array depth. In reg [7:0] mem [0:255], the 8 refers to bits per word, and 256 is the number of words.