Verilog Module Structure

In Verilog, every design begins with a module. The module is the fundamental building block of any hardware description, encapsulating ports, internal logic, and instantiations of other modules into a single named unit that maps directly to a physical hardware entity.

Understanding module structure is the starting point for all digital design in Verilog. GATE aspirants frequently encounter questions on port declarations, module instantiation syntax, and hierarchical connectivity, making this one of the highest-priority topics in HDL-based questions.

Core Concept: The Module Block

A module in Verilog is the basic unit of design, equivalent to a circuit block or a chip in hardware. It always begins with the keyword module followed by a unique module name, and ends with the keyword endmodule. Everything between these two keywords defines the behavior and structure of the hardware block.

The port list comes immediately after the module name inside parentheses. Ports can be declared as input, output, or inout. In Verilog-2001 and later, the direction and data type are declared directly inside the port list, simplifying the code considerably compared to older Verilog-1995 style where ports were declared separately below the port list.

Inside the module body, a designer can write continuous assignments using assign, instantiate other modules, or write procedural blocks such as always and initial. These elements together fully describe the hardware the module represents.

Port Declaration Syntax

Port declarations specify the direction and type of each signal that crosses the module boundary. In Verilog-2001 ANSI style, the full declaration is written in the port list itself. A port declared as input wire clk means the signal enters the module and is a net type. An output reg q means the signal leaves the module and is driven by a procedural block such as an always block. The distinction between wire and reg at the output is a very common GATE trap.

For multi-bit ports, the bit width is specified using a range notation. For example, input [7:0] data_in declares an 8-bit wide input port. The leftmost index is the most significant bit. This notation is called a vector port and is used extensively when designing buses and datapaths.

Module Instantiation and Hierarchy

One module can be used inside another module through module instantiation. This creates a hierarchical design where a top-level module contains instances of smaller sub-modules, mirroring how physical chips contain smaller functional blocks. Instantiation uses the syntax: module_name instance_name (.port(signal)); where port names are explicitly connected using named port mapping.

Named port mapping is always preferred over positional port mapping in practice because it is less error-prone and more readable. In positional mapping, signals are connected in the exact order the ports were declared in the sub-module, which can lead to silent connection errors if port order is changed later.

Mathematical Expression: Port Count and Connectivity

While module structure itself is syntactic, there is a useful design rule for hierarchical connectivity. If a module has N input bits and M output bits, the total wire count crossing the module boundary is N + M. For a hierarchical design with K identical instances, the total number of port connections in the parent module is K x (N + M). This becomes important when estimating routing complexity in larger designs and is occasionally asked in GATE context problems.

Solved Numerical Example

A top-level module instantiates three identical sub-modules. Each sub-module has 2 input ports and 1 output port. Calculate the total number of named port connections required in the top-level module for all three instances using named port mapping.

Given:
Number of sub-module instances (K) = 3
Inputs per instance (N) = 2
Outputs per instance (M) = 1

Why this formula applies:
Each instantiation requires one named connection per port.
Total connections = K x (N + M)

Formula:
Total port connections = K x (N + M)

Substitution:
Total = 3 x (2 + 1)

Calculation:
Total = 3 x 3 = 9

Final Answer:
9 named port connections are required in the top-level module.

Exam Tip: In GATE questions, if an output port is driven by an always block, it must be declared as reg. If driven by assign, it must be wire. Confusing this is the most common Verilog trap in objective questions.

Practical Implication

In real FPGA and ASIC design flows, the module boundary defines the synthesis unit. Each module is synthesized independently and then linked. Keeping modules small and well-defined improves synthesis quality, enables easier simulation, and simplifies testbench writing. Industry tools like Vivado and Quartus treat each module as a logic cone for optimization purposes.

• Each instance is a separate hardware copy. Instances u1, u2, u3 each represent distinct logic blocks even though they share the same module definition.
• Named port mapping syntax .port_name(signal_name) prevents misconnection errors that occur with positional mapping.
• The parent module uses wire signals to carry values between instances and to the top-level ports.
• Instance names (u1, u2, u3) are unique identifiers used by simulation tools to trace signal paths through hierarchy.
• The sub-module definition exists once in code but is physically replicated once per instantiation during synthesis.

Quick Revision

• A Verilog module begins with module module_name (port_list); and ends with endmodule. Nothing exists outside this block.
• Ports are declared as input, output, or inout. In ANSI style (Verilog-2001), direction and type are declared inside the port list directly.
• Key trap: output driven by always block must be reg. Output driven by assign must be wire.
• Module instantiation syntax: module_name instance_name (.port(signal)); Named mapping is preferred over positional mapping.
• Total port connections for K instances with N inputs and M outputs = K x (N + M).
• Hierarchy allows reuse. The same module definition can be instantiated multiple times without rewriting the logic.
• inout ports are used for bidirectional signals such as I2C SDA lines and require special tri-state handling using bufif or assign with high-Z.