Verilog Operators

Operators in Verilog perform computations on signals and constants, directly determining how logic is synthesized into hardware gates. Every operator has a specific hardware interpretation, and using the wrong operator type can produce unexpected logic or synthesis errors. Mastery of all operator categories is essential for both coding correctness and GATE preparation.

Verilog provides six major operator categories: arithmetic, logical, bitwise, reduction, shift, and concatenation. GATE questions frequently test the difference between logical and bitwise operators, the behavior of reduction operators, and the output width rules for arithmetic and shift operations.

Arithmetic Operators

Verilog arithmetic operators (+, -, *, /, %) perform integer math on vectors. The result width equals the width of the widest operand, unless the result is assigned to a wider variable. This means arithmetic overflow occurs silently when the mathematical result exceeds the declared bit width. For example, adding two 4-bit values that sum to more than 15 will lose the carry bit unless the destination is at least 5 bits wide. The exponentiation operator ** is available but is rarely synthesizable and is mainly used in testbench parameter calculations.

Logical Versus Bitwise Operators

This is the most commonly confused pair of operator categories. Logical operators (&&, ||, !) treat each operand as a single boolean value: if the operand is non-zero it is treated as true, if zero it is treated as false. The result is always a single bit, either 0 or 1. Bitwise operators (&, |, ~, ^, ~^) operate independently on corresponding bits of two multi-bit operands and return a result of the same width. So 4'b1100 & 4'b1010 = 4'b1000 while 4'b1100 && 4'b1010 = 1 because both operands are non-zero.

Reduction Operators

Reduction operators are unary operators that fold all bits of a single vector into a single bit result by applying the operation across all bits from bit 0 to the MSB. &data gives 1 only if all bits of data are 1 (reduction AND). |data gives 1 if any bit is 1 (reduction OR). ^data gives 1 if an odd number of bits are 1 (reduction XOR, commonly used for parity generation). These are synthesized to multi-input gate trees and are highly area-efficient for parity and zero-detect logic.

Shift Operators

Verilog provides logical shift operators << and >> which shift bits and fill vacated positions with zeros. The arithmetic shift operators <<< and >>> are sign-aware. For arithmetic right shift (>>>), if the operand is a signed value, the vacated MSB positions are filled with the sign bit to preserve the sign of a two's complement number. For unsigned values, >>> behaves identically to >>. The result width of a shift operation equals the width of the left operand regardless of the shift amount.

Concatenation and Relational Operators

The concatenation operator {} joins multiple signals or constants into a wider vector. {a, b} where a is 4 bits and b is 4 bits creates an 8-bit result with a as the upper nibble. The replication operator {N{expr}} repeats expr exactly N times. Relational operators (==, !=, <, >, <=, >=) return a 1-bit result. The case equality operators === and !== also compare x and z values exactly, unlike == which returns x if either operand contains x. This distinction is important in simulation verification.

Mathematical Expression: Operator Precedence

Verilog operator precedence follows a well-defined order from highest to lowest: unary operators (!, ~, reduction), then arithmetic (* / %), then additive (+ -), then shift (<< >>), then relational (< > <= >=), then equality (== !=), then bitwise (&, ^, |), then logical (&& ||), and finally the conditional operator (?:). When in doubt, parentheses should always be used to make precedence explicit and avoid synthesis mismatches between the intended and actual logic.

Solved Numerical Example

Given two 4-bit values A = 4'b1010 and B = 4'b0110, evaluate the results of bitwise AND, reduction XOR on A, logical OR, and a left shift of A by 2. State the bit width of each result.

Given:
A = 4'b1010  (decimal 10)
B = 4'b0110  (decimal 6)

Why this formula applies:
Bitwise &: operates bit-by-bit, same width as operands.
Reduction ^A: XOR all bits of A, result is 1 bit.
Logical ||: boolean OR of whole values, result is 1 bit.
Shift <<: A shifted left, result is same width as A (4 bits).

Formula:
A & B       = AND each bit pair
^A          = XOR all bits of A
A || B      = 1 if either is non-zero
A << 2      = shift A left by 2, zero-fill right

Substitution and Calculation:
A &  B  = 1010 & 0110 = 0010  (4-bit result)
^A      = 1 XOR 0 XOR 1 XOR 0 = 0  (1-bit result)
A || B  = (1010 != 0) || (0110 != 0) = 1 || 1 = 1  (1-bit result)
A << 2  = 1010 << 2 = 1000  (4-bit, upper bits lost)

Final Answers:
A & B  = 4'b0010 (4-bit)
^A     = 1'b0    (1-bit, even parity)
A || B = 1'b1    (1-bit)
A << 2 = 4'b1000 (4-bit, carry lost)

Exam Tip: The single biggest GATE trap in operators is confusing & (bitwise) with && (logical) and | (bitwise) with || (logical). Bitwise gives a multi-bit result. Logical always gives a 1-bit boolean. Also remember: === matches x and z exactly, while == returns x if any operand bit is x. Use === only in simulation, never for synthesis.

Practical Implication

Reduction XOR is synthesized as a parity tree and is used directly in CRC generators, ECC memory controllers, and error detection circuits. Shift operators synthesize to routing-only structures (no logic gates needed for constant shifts), making them extremely efficient. Concatenation and replication operators synthesize purely as wire rearrangements with zero gate cost, making them fundamental to bus manipulation in datapath designs.

• Bitwise AND (&) operates on corresponding bits of two equally-wide operands and returns a result of the same width.
• Logical AND (&&) reduces each operand to a boolean (0 if zero, 1 if non-zero) and returns a single 1-bit result.
• Reduction XOR (^A) is unary: it XOR-reduces all bits of a single vector into one bit. Used for parity generation.
• Arithmetic shift right (>>>) fills with sign bit for signed variables, preserving two's complement value. Logical shift right (>>) always fills with 0.
• Case equality (===) matches all four logic values including x and z. Regular equality (==) returns x if any operand bit is x. Use === only in simulation.

Quick Revision

• Arithmetic operators (+, -, *, /, %): result width equals widest operand. Overflow is silently truncated. Assign to a wider variable to capture carry.
• Bitwise vs Logical: & | ^ are bitwise (multi-bit result). && || ! are logical (always 1-bit boolean result).
• Reduction operators (&, |, ^, ~&, ~|, ~^) are unary. They fold all bits of one vector into a single bit.
• Shift: << and >> are logical (fill with 0). <<< and >>> are arithmetic (>>> fills with sign bit for signed types).
• Concatenation {a,b,c}: joins signals, width = sum of all operand widths. Replication {N{expr}}: repeats expr N times.
• Key trap: == returns x if any bit of either operand is x. === matches x and z exactly. Use === for testbench checks involving unknown values.
• Operator precedence: unary > arithmetic > shift > relational > equality > bitwise > logical > conditional. Always use parentheses to make intent explicit.