CMOS NAND/NOR

The CMOS NAND gate is constructed by combining a series-connected nMOS pull-down network with a parallel-connected pMOS pull-up network. Similarly, a CMOS NOR gate uses parallel nMOS and series pMOS networks. Understanding the series-parallel duality between pull-up and pull-down networks, and the transistor sizing implications, is central to CMOS logic design and is a high-frequency topic in GATE examinations.

Core Concept Explanation

In complementary CMOS logic, every gate has two networks: the Pull-Down Network (PDN) made of nMOS transistors that connects the output to GND when the output should be low, and the Pull-Up Network (PUN) made of pMOS transistors that connects the output to VDD when the output should be high. The fundamental rule of CMOS gate construction is that PDN and PUN are always dual networks — wherever the PDN has transistors in series, the PUN has them in parallel, and vice versa.

For a NAND gate, the output is low (logic 0) only when all inputs are high. This means all nMOS transistors must be ON simultaneously — which requires a series connection in the PDN. By duality, the PUN has all pMOS transistors in parallel, so the output is pulled to VDD whenever any input is low. For a NOR gate, the output is low when any input is high, so the PDN has nMOS transistors in parallel, and by duality the PUN has pMOS transistors in series.

This duality principle is not just a design trick — it guarantees that PUN and PDN are never simultaneously ON in steady state (no direct path from VDD to GND), and that at least one network is always ON (output is always driven). These two properties ensure zero static power and full-swing output, which are the defining advantages of complementary CMOS.

Transistor Sizing for Series Networks

When transistors are placed in series, the effective drive strength of the series stack is reduced compared to a single transistor. For n transistors of width W in series, the combined resistance is approximately n times the resistance of a single transistor of width W. To maintain the same drive current (and hence the same delay) as an inverter, each transistor in a series stack of n devices must be sized with width n×W where W is the reference inverter transistor width.

This sizing rule has an important consequence for NAND vs NOR gates. In a 2-input NAND, the PDN has 2 nMOS transistors in series — so each must be 2×Wn (twice the minimum nMOS width) to match inverter drive strength. The PUN has 2 pMOS transistors in parallel — each can remain at Wp (the standard pMOS width, already 2–3× Wn for mobility matching). For a 2-input NOR gate, the PUN has 2 pMOS in series — each must be 2×Wp, which is 4–6× Wn. This makes NOR gates significantly larger in area than NAND gates of the same fanin, and this is why NAND gates are preferred in CMOS synthesis over NOR gates.

The worst-case path for timing analysis in a CMOS gate is the path through the series-connected network. For a 2-input NAND, the worst-case pull-down is when both inputs switch high simultaneously. For a 3-input NAND, the worst-case involves all three nMOS transistors in series, which is why large fan-in NAND gates suffer significant delay and require more aggressive sizing.

Practical Understanding

The body effect is an important concern for series-connected transistors. In a NAND pull-down network with nMOS in series, the transistor whose source is not connected directly to GND experiences body effect — its source voltage rises above GND as the stack pulls down, increasing the threshold voltage Vth of that transistor. This further weakens the pull-down and increases the switching delay compared to a simple two-transistor resistance estimate. Process technologies use body ties or triple-well processes to mitigate body effect in series stacks.

For layout and area efficiency, NAND gates are inherently more compact than NOR gates because the series pMOS stack in NOR requires larger device widths to compensate for low hole mobility. In standard cell libraries, a 2-input NAND typically occupies 1.33× the area of an inverter, while a 2-input NOR occupies about 1.67× due to the wider pMOS requirement. This drives modern synthesis tools to preferentially map logic into NAND-based networks.

Given:
Reference inverter: nMOS W/L = 1µm/0.18µm, pMOS W/L = 2µm/0.18µm
Mobility ratio: µn/µp = 2, so Wp = 2×Wn for balanced inverter.
Design a 2-input NAND gate with same drive strength as the inverter.

Why this formula applies:
Series stack of N transistors → each transistor width must be N × W_reference
to maintain equivalent drive current (same on-resistance as single transistor).

Formula:
W_series = N × W_reference

For NAND PDN (2 nMOS in series):
W_nMOS_NAND = 2 × 1µm = 2µm (each nMOS)

For NAND PUN (2 pMOS in parallel):
W_pMOS_NAND = 2µm (each pMOS, unchanged — parallel does not degrade drive)

For NOR PDN (2 nMOS in parallel):
W_nMOS_NOR = 1µm (each nMOS, unchanged)

For NOR PUN (2 pMOS in series):
W_pMOS_NOR = 2 × 2µm = 4µm (each pMOS)

Final Answer:
NAND: nMOS = 2µm each, pMOS = 2µm each. Total W = 2+2+2+2 = 8µm
NOR:  nMOS = 1µm each, pMOS = 4µm each. Total W = 1+1+4+4 = 10µm
NAND is ~20% smaller than NOR in this case, confirming CMOS preference for NAND gates.

Exam Tip: In GATE, for sizing questions: series nMOS in NAND require 2× width (for 2-input) but series pMOS in NOR require 2× of already-larger pMOS, making NOR gates much larger. Also remember — body effect further slows series stacks but is not captured in simple resistance models.

Quick Revision

• CMOS gate rule: PDN (nMOS) and PUN (pMOS) are always dual networks. Series in PDN means parallel in PUN and vice versa.
• NAND: PDN = series nMOS, PUN = parallel pMOS. Output is 0 only when all inputs = 1.
• NOR: PDN = parallel nMOS, PUN = series pMOS. Output is 0 when any input = 1.
• Series sizing rule: W_series = N × W_reference. Each device in an N-transistor series stack must be N× wider.
• NAND preferred over NOR: NOR's series pMOS is already wide (2–3× nMOS) and must be doubled again, making it 4–6× Wn per transistor vs 2× Wn for NAND's series nMOS.
• Body effect worsens delay in series stacks — source of non-grounded nMOS rises above GND, increasing Vth.
• GATE trap: Parallel transistors do NOT require wider sizing — only series stacks require width scaling for drive strength matching.