D Latch

A D latch is the most fundamental level-sensitive storage element in digital design. Unlike combinational circuits that produce outputs purely from present inputs, a latch retains state, making it the building block of all sequential VLSI systems. Understanding how a D latch works at the transistor level is essential for GATE and for designing real static CMOS circuits.

Core Concept Explanation

A latch is a level-sensitive device. The word level-sensitive means the output changes in direct response to the input as long as the control signal (clock) remains at a particular level. When the clock is high, the latch is transparent and Q simply follows D. When the clock goes low, whatever value Q held at that moment is frozen, and the latch enters a hold state.

This is fundamentally different from a flip-flop, which changes state only at a clock edge. The level-sensitive nature of a latch introduces the concept of glitch propagation: if D changes multiple times while CLK is high, Q will follow all those transitions, making the latch unsuitable where glitch-free sequential behavior is needed.

In CMOS, the D latch is most elegantly implemented using a transmission gate (TG) and an inverter-based feedback loop. A transmission gate consists of one NMOS and one PMOS transistor connected in parallel between the same two nodes. When enabled, it passes the input to the output with very low resistance and near-rail voltage levels, which makes it superior to a single pass transistor.

The standard CMOS D latch uses two transmission gates. When CLK is high, TG1 is enabled and TG2 is disabled. The data D passes through TG1, through an inverter, and reaches Q. When CLK goes low, TG1 is cut off and TG2 is enabled, forming a feedback loop through two inverters. This cross-coupled inverter pair holds the stored bit indefinitely, consuming zero static power.

Mathematical Expression and Behavior

The Boolean behavior of a D latch is described by the characteristic equation:

Q(next) = D, when CLK = 1

Q(next) = Q(current), when CLK = 0

In terms of transistor sizing, the transmission gate must be sized to drive the inverter load correctly. The on-resistance of a transmission gate is approximately Ron = 1 / (kn * (Vgs - Vth)), and both NMOS and PMOS are sized so that the combined parallel resistance is low enough to charge or discharge the load within the intended propagation delay budget.

The propagation delay of the latch, denoted t_pd, includes the TG delay and the inverter delay. Typically for a standard cell D latch in 180nm CMOS, t_pd is around 200 to 400 ps depending on load capacitance.

Practical Understanding

In real VLSI design, D latches are used inside pipeline stages as part of a two-phase non-overlapping clock scheme. A master latch opens on phase 1 and a slave latch opens on phase 2, together forming a flip-flop. This architecture is used in standard cell libraries from TSMC, UMC, and other foundries.

One critical practical concern is the latch transparency window, which is the period CLK stays high. If this window is too wide and D has glitches, erroneous data can propagate. In dynamic CMOS pipelines, this is carefully controlled. Another concern is charge sharing on the internal nodes of the latch during switching, which can corrupt the stored value.

The transmission gate latch uses approximately 12 transistors in its full CMOS form with feedback, making it compact for integration in dense sequential logic arrays.

Given:
CLK pulse width (transparency window) = 2 ns
D input changes 3 times during CLK=1: D = 0 → 1 → 0 → 1
Final D value when CLK falls = 1

Why this formula applies:
D latch is level-sensitive, so Q follows D while CLK=1
When CLK falls, Q stores the last value of D

Formula:
Q = D (while CLK=1)
Q_stored = D at falling edge of CLK

Substitution:
During CLK=1: Q transitions 0 → 1 → 0 → 1 (all visible)
At CLK falling edge: D = 1

Calculation:
Q_stored = 1

Final Answer: Q = 1 after CLK goes low. All intermediate transitions were propagated during transparency window, but only final state is retained.

Exam Tip: GATE frequently tests whether a latch is edge-triggered or level-triggered. A D latch is level-sensitive — Q = D only while CLK=1. If D changes 4 times during CLK=1, Q also changes 4 times. This is the key distinguisher from a D flip-flop.

Quick Revision

• D latch is level-sensitive: Q = D when CLK = 1, Q holds when CLK = 0.
• Implemented in CMOS using two transmission gates and two inverters (cross-coupled for hold).
• Transmission gate = NMOS + PMOS in parallel; passes near-ideal voltage levels.
• During CLK=1 (transparent phase), glitches on D appear on Q — this is a design risk.
• Two D latches with complementary clocks form one D flip-flop (master-slave).
• Formula recall: Q_next = D (CLK=1), Q_next = Q_current (CLK=0).
• Trap: Do not confuse latch transparency with flip-flop clock edge sensitivity in GATE problems.