Domino Logic Circuits

In high-speed VLSI design, static CMOS gates consume considerable area and have limited speed when cascaded. Domino logic was introduced to overcome these limitations by using a two-phase clocked scheme that allows fast evaluation of logic functions with fewer transistors and higher operating frequencies.

Core Concept of Domino Logic

Domino logic is a clocked dynamic CMOS logic family that replaces the static pull-up PMOS network with a single PMOS precharge transistor and replaces the output stage with a static CMOS inverter. The operation is divided into two distinct phases controlled by a clock signal.

During the precharge phase (CLK = 0), the PMOS transistor connected to VDD turns ON and charges the dynamic output node to VDD. Simultaneously, the NMOS foot transistor at the bottom of the pull-down network (PDN) is turned OFF, preventing any discharge path. This ensures the output node is reset to a known high state before logic evaluation begins.

During the evaluate phase (CLK = 1), the PMOS precharge transistor turns OFF and the NMOS foot transistor turns ON. The PDN can now conduct if the logic inputs satisfy the discharge condition. If the PDN conducts, the dynamic node discharges to GND; if not, it remains at VDD. The following static inverter buffers this output for the next stage.

A critical property of domino logic is that outputs are monotonically non-decreasing during evaluation: an output can only transition from 0 to 1 (at the inverter output), never from 1 to 0 within one evaluate phase. This monotone behavior allows cascading domino stages without race conditions, similar to how dominoes fall in sequence, which gives the logic family its name.

Cascade Issues and the Role of the Inverter

A bare dynamic CMOS gate without the output inverter cannot be cascaded directly because its output is high during precharge regardless of logic inputs, and a subsequent stage's PDN would see a spurious high signal and might incorrectly discharge. The static inverter after each dynamic node solves this by converting the active-low dynamic node to an active-high stable output, enabling cascade chains.

However, cascading introduces a fundamental limitation: only non-inverting logic functions can be implemented in a single domino stage. Functions requiring inversion (such as XNOR directly) require restructuring the PDN or using two cascaded stages. Additionally, because the foot transistor adds a series NMOS device, the charge sharing problem becomes relevant when internal nodes of the PDN hold parasitic charge that can partially discharge the output node even without a full logic-1 path.

Mathematical Expression

The key timing constraint in domino logic relates to the precharge and evaluate time. The output node capacitance C must be fully precharged within the precharge period and must evaluate (discharge if required) within the evaluate period. For the discharge path, the discharging time constant is approximately:

t_discharge = C_out / (k_n x (W/L) x (VDD - V_th)^2 / 2) for saturation region initially, transitioning to linear. A simpler design estimate uses: t_eval = C_out x V_swing / I_discharge_avg. This sets the minimum required NMOS sizing in the PDN to guarantee evaluation within one half-cycle.

Practical Understanding

Domino logic reduces the transistor count significantly compared to complementary CMOS. A static CMOS gate implementing an N-input AND requires 2N transistors (N PMOS + N NMOS). The equivalent domino implementation requires only N+2 transistors (N NMOS in PDN + 1 PMOS precharge + 1 NMOS foot) plus the 2-transistor inverter, totaling N+4. For large N, this is a substantial saving.

The absence of a complementary PMOS pull-up network also removes the series PMOS resistance bottleneck, allowing faster evaluation for complex functions. This is why domino logic is preferred in high-performance arithmetic units such as adders and multipliers in modern processors. The clock overhead is the trade-off: every stage requires a global clock, increasing clock tree complexity and power.

Leakage current is a concern in domino logic at deep submicron nodes. During the evaluate phase, if the dynamic node is not discharged (output should stay high), sub-threshold leakage through OFF NMOS transistors can slowly pull down the dynamic node voltage over time. This imposes a maximum evaluate window and limits the use of domino logic in low-frequency or standby-heavy applications.

Given:
Output node capacitance C_out = 50 fF
VDD = 1.2 V, V_th(NMOS) = 0.3 V
NMOS W/L = 4, k_n = 200 uA/V^2
Clock frequency f = 1 GHz, evaluate window T_eval = 0.5 ns

Why this formula applies:
We check if the PDN can discharge C_out within T_eval using average current approximation.

Formula:
I_avg = (k_n / 2) x (W/L) x (VDD - V_th)^2

Substitution:
I_avg = (200e-6 / 2) x 4 x (1.2 - 0.3)^2

Calculation:
I_avg = 100e-6 x 4 x 0.81
I_avg = 324 uA

t_discharge = C_out x VDD / I_avg
t_discharge = 50e-15 x 1.2 / 324e-6
t_discharge = 0.185 ns

Final Answer:
t_discharge = 0.185 ns, which is less than T_eval = 0.5 ns.
The PDN successfully discharges within the evaluate window. Design is valid.

Exam Tip: In GATE, domino logic questions often test whether you know that only NON-INVERTING functions can be directly cascaded in standard domino gates, and that an inverter must follow each dynamic stage. Charge sharing is a common trap question.

Mechanism of Domino Logic

• Precharge phase (CLK=0): PMOS charges output node to VDD; NMOS foot is OFF; PDN cannot evaluate.
• Evaluate phase (CLK=1): PMOS turns OFF; NMOS foot turns ON; PDN either discharges output to 0 or holds it at VDD.
• The static inverter after the dynamic node buffers the output and enables monotone cascade: next stage receives a 0-to-1 transition only.
• Charge sharing occurs when internal PDN nodes hold charge that redistributes with C_out during evaluation, causing incorrect partial discharge.
• Solutions to charge sharing include keeper transistors (weak PMOS feedback) and careful sizing of PDN transistors to ensure C_int is much smaller than C_out.
• Domino gates can only implement non-inverting Boolean functions directly; AND, OR, and their complex combinations are straightforward; NAND and NOR require restructuring.

Quick Revision

• Domino logic uses two phases: precharge (CLK=0, output=VDD) and evaluate (CLK=1, PDN discharges or holds).
• Structure: 1 PMOS precharge + PDN (N NMOS) + 1 NMOS foot + 1 static CMOS inverter per stage.
• Key formula for discharge check: t_discharge = C_out x VDD / I_avg where I_avg = (k_n/2)(W/L)(VDD-Vth)^2.
• Only non-inverting functions can be cascaded; inverter after each stage ensures monotone transitions.
• Charge sharing: internal node capacitance C_int redistributes with C_out, reducing output voltage incorrectly.
• Keeper transistor (weak PMOS) is the standard fix for both charge sharing and leakage in evaluate phase.
• GATE trap: domino logic is not a static logic family — it cannot hold state without a clock; it is sensitive to leakage at long evaluate windows.