FinFET Technology

As planar MOSFET scaling approached the 22 nm node, the fundamental limitation of a single-gate controlling a short channel became insurmountable. Short-channel effects including DIBL and sub-threshold slope degradation prevented further scaling with acceptable leakage. FinFET (Fin Field-Effect Transistor) technology introduced a three-dimensional gate structure that wraps around a thin silicon fin, restoring strong gate control and enabling continued scaling below 22 nm. FinFETs are the standard transistor architecture at 16 nm, 10 nm, 7 nm, and beyond.

Core Concept Explanation

In a planar MOSFET, the gate electrode sits above a wide flat channel region. As channel length shrinks, the depletion regions of the source and drain extend further into the channel and begin to control the channel potential directly, reducing the gate's influence. This is the origin of short-channel effects (SCEs) such as V_T roll-off, DIBL, and increased sub-threshold slope. These effects increase leakage dramatically and make the transistor difficult to turn off.

FinFET addresses this by forming the channel as a thin vertical silicon fin. The gate electrode wraps around the fin on three sides (top and two sides), a configuration called tri-gate. With gate oxide on three surfaces, the gate exerts much stronger electrostatic control over the entire fin cross-section. The thin fin geometry also reduces the volume available for source and drain depletion regions to encroach, inherently suppressing DIBL and V_T variation.

The effective channel width in a FinFET is determined by the fin height (H_fin) and pitch. For a transistor with N fins, the effective width is approximately W_eff = N × (2 × H_fin + W_fin) where W_fin is the fin width. Since width is set by the number of fins (quantized), FinFET sizing is discrete rather than continuous as in planar CMOS. Standard cell design must account for this quantization when targeting specific drive strengths.

Mathematical Expression

The sub-threshold slope (SS) describes how sharply a transistor turns off below threshold. For an ideal MOSFET, the theoretical minimum is SS = n × (kT/q) × ln(10) ≈ 60 mV/decade at 300 K where n is the body effect coefficient. For planar MOSFETs with short channels, n increases due to poor gate control and SS can reach 100 to 150 mV/decade, meaning the transistor leaks significantly even well below V_T.

FinFETs with fully depleted thin fins approach the ideal SS of 60 mV/decade because the gate controls the entire fin body with negligible body effect (n close to 1). A steeper SS means lower leakage at any given V_T, or equivalently, lower V_T (and thus higher drive current and speed) can be used while maintaining acceptable leakage. This is why FinFETs simultaneously deliver better performance and lower power compared to planar devices at the same technology node.

Practical Understanding

FinFET fabrication is significantly more complex than planar CMOS. The fins are patterned using Self-Aligned Double Patterning (SADP) or EUV lithography to achieve fin pitches below 30 nm. The gate is then deposited around the fin using high-k metal gate (HKMG) stack, the same material improvement that was introduced for planar devices at 45 nm. CMP and deposition steps are more numerous and tighter in specification.

V_T in FinFET is set primarily by the metal gate work function rather than channel doping, because the thin fully-depleted fin cannot sustain the high doping concentrations used in planar devices. Different metal alloys or gate stacks are deposited for NMOS and PMOS to achieve the desired V_T values. Multi-Vt FinFET cells use different gate metal compositions to realize HVT, SVT, and LVT flavors within the same process.

The main challenges in FinFET design include fin resistance, parasitic capacitances at fin corners, and the quantized width constraint. At very advanced nodes (3 nm and below), the industry is transitioning to Gate-All-Around (GAA) transistors such as nanosheets and nanowires, which extend gate wrapping to all four sides of the channel, offering even better electrostatic control than FinFET.

Given:
FinFET process: H_fin = 40 nm, W_fin = 7 nm
Number of fins = 3
Compare W_eff to planar transistor of W = 120 nm

Why this formula applies:
FinFET effective width set by fin geometry and count

Formula:
W_eff = N × (2 × H_fin + W_fin)

Substitution:
W_eff = 3 × (2 × 40 + 7) nm
      = 3 × (80 + 7) nm
      = 3 × 87 nm

Calculation:
W_eff = 261 nm

Final Answer: W_eff = 261 nm

Note: Planar W = 120 nm gives continuous sizing
FinFET W jumps: 1 fin → 87 nm, 2 fins → 174 nm, 3 fins → 261 nm
Designer must choose nearest valid multiple. Width is quantized.

Exam Tip: FinFET width is quantized in multiples of (2×H_fin + W_fin). GATE may ask for W_eff given fin dimensions. Also remember: FinFET achieves near-ideal sub-threshold slope of 60 mV/decade because the fully depleted fin makes the body effect coefficient n close to 1.

FinFET Structure and Short Channel Suppression Mechanism

• FinFET uses a thin vertical silicon fin as the channel. The gate wraps on three sides (tri-gate), giving the gate dominant electrostatic control and suppressing source and drain depletion encroachment.
• Sub-threshold slope in FinFET approaches the ideal 60 mV/decade limit because the thin fully-depleted fin eliminates the body effect, setting n close to 1 in the SS formula.
• Effective width is quantized: W_eff = N × (2·H_fin + W_fin). Standard cell sizing must use integer fin counts, which requires careful multi-height cell library design.
• Threshold voltage is set by the metal gate work function, not channel doping, enabling tight V_T control across multi-Vt cell flavors using different gate metal compositions.
• DIBL is suppressed because the thin fin geometry limits the drain depletion region's lateral reach into the channel, maintaining V_T stability with V_DS variation.
• Gate-All-Around (GAA) nanosheet transistors are the successor to FinFET at 3 nm and below, wrapping the gate on all four sides for even stronger electrostatic control.

Quick Revision

• FinFET = thin vertical Si fin + tri-gate. Gate on 3 sides restores electrostatic control lost in short-channel planar devices.
• W_eff = N × (2·H_fin + W_fin). Width is quantized by fin count. Key formula for GATE numerical problems.
• SS ≈ 60 mV/decade in FinFET vs 100–150 mV/decade in short-channel planar. Steeper SS means lower leakage at same V_T.
• V_T set by metal gate work function (not doping). Multi-Vt achieved by different gate metal alloys.
• DIBL suppressed by thin fin geometry. Short channel effects dramatically reduced compared to planar CMOS.
• Exam trap: FinFET width is NOT continuous. Designers cannot set arbitrary width — must use integer multiples of single-fin width. This is a major design constraint.
• Next generation: GAA nanosheets (4-side gate wrap) at 3 nm and below. FinFET remains dominant at 16 nm through 5 nm nodes.