Hot Carrier Effect

As MOSFET channel lengths shrink into the deep submicron regime, the electric field across the channel rises dramatically. This intense field imparts enough energy to carriers that they no longer remain in thermal equilibrium with the lattice, giving rise to the Hot Carrier Effect — a critical reliability concern in modern VLSI design. Understanding this phenomenon is essential for GATE aspirants and anyone working with short-channel MOS devices.

Core Concept Explanation

In a long-channel MOSFET, the lateral electric field along the channel is moderate and carriers travel at drift velocities proportional to that field. As channel length decreases, the same supply voltage VDS produces a far higher lateral field because the field scales roughly as VDS/L. Carriers accelerated by this field gain kinetic energy well above the thermal energy kT of the lattice. These energetic carriers are called hot carriers because they behave as if they exist at a much higher effective temperature.

Near the drain end of the channel, where the field is strongest (the pinch-off region), hot electrons (in nMOS) can initiate impact ionization. In this process, a single energetic electron collides with a silicon lattice atom and knocks out an electron-hole pair. The generated holes drift toward the substrate, constituting a substrate current Isub. This current is an indirect but measurable indicator of hot carrier activity and is routinely monitored during reliability testing.

A fraction of the hot electrons have enough energy to surmount the Si-SiO2 barrier (approximately 3.2 eV) and get injected into the gate oxide. Once inside the oxide, these electrons either get trapped at existing defect sites or create new interface traps at the Si-SiO2 interface. Both effects permanently alter the threshold voltage and degrade carrier mobility over time. This time-dependent degradation is the core reliability concern known as Hot Carrier Injection (HCI).

The degradation is asymmetric: it is most severe near the drain because that is where the electric field peaks and where injection predominantly occurs. This spatial asymmetry matters because if such a transistor is later operated in reverse (source and drain swapped), the degraded region is now near the source and the threshold voltage shift behaves differently.

Mathematical Expression

The substrate current generated by impact ionization is modeled empirically as:

Isub = A · IDS · exp(−B / (VDS − VDsat))

Here, A and B are process-dependent constants, IDS is the drain current, VDS is the drain-source voltage, and VDsat is the saturation voltage. The exponential term captures the strong sensitivity of impact ionization to the lateral electric field. The product A · IDS represents the available current that participates in ionization, while the exponential describes the probability of each carrier causing an ionization event.

The lifetime of the device under HCI stress is often characterized using the empirical relation: τ ∝ (Isub/IDS)^(−n), where n is a process-specific exponent typically between 2 and 4. A lower Isub/IDS ratio implies a longer device lifetime, which directly motivates the use of Lightly Doped Drain (LDD) structures that spread out the peak field and reduce Isub.

Practical Understanding

The Hot Carrier Effect manifests practically as a gradual shift in the MOSFET threshold voltage Vth and a reduction in transconductance gm over time. For digital circuits, a rising Vth in nMOS transistors increases propagation delay. For analog circuits, degrading gm directly impairs gain and bandwidth. These are not sudden failures but slow parametric degradations that accumulate over the device's operational lifetime, typically defined as 10 years for consumer electronics.

Several design and process techniques mitigate HCI. The LDD structure introduces a lightly doped region between the channel and the heavily doped drain, spreading the peak field over a larger distance and reducing its magnitude. Reducing the supply voltage VDD is the most effective remedy since the lateral field drops proportionally. Drain Engineering techniques such as halo implants and asymmetric source-drain doping also help manage the field distribution. In modern FinFETs and GAA (Gate All Around) architectures, the three-dimensional electrostatic control of the channel inherently reduces short-channel effects and mitigates HCI.

From a circuit design perspective, hot carrier reliability imposes constraints on the maximum operating voltage. Foundry PDKs specify maximum VDS and VGS values for each transistor type and size, and exceeding these limits accelerates HCI degradation. Reliability-aware design methodologies perform electromigration and hot-carrier stress analysis as standard steps in the signoff flow.

Given:
Channel length L = 0.18 µm, VDS = 1.8 V, VDsat = 0.9 V
Process constants: A = 1.2 × 10^3 V^-1, B = 4.5 × 10^6 V/m (expressed as 1.5 V in this normalized model)
Drain current IDS = 500 µA

Why this formula applies:
The substrate current from impact ionization is modeled by Isub = A · IDS · exp(−B_eff / (VDS − VDsat))
where B_eff = 1.5 V is the normalized ionization threshold for this process.

Formula:
Isub = A · IDS · exp(−B_eff / (VDS − VDsat))

Substitution:
Isub = 1.2×10^3 × 500×10^-6 × exp(−1.5 / (1.8 − 0.9))
Isub = 0.6 × exp(−1.5 / 0.9)
Isub = 0.6 × exp(−1.667)

Calculation:
exp(−1.667) ≈ 0.1889
Isub = 0.6 × 0.1889 = 0.1133 A × 10^0
Isub ≈ 113.3 µA

Final Answer:
Isub ≈ 113 µA
Isub/IDS = 113/500 = 0.226
This high ratio (>0.1) indicates significant hot carrier stress; LDD or VDD reduction is needed.

Exam Tip: In GATE problems, the substrate current Isub is the key indicator of hot carrier activity. Maximum Isub occurs not at maximum VGS but near VGS ≈ VDS/2 + Vth, because this condition maximizes the product of available carriers and ionization probability. Do not confuse Isub with IDS.

Mechanism and Effects Summary

The sequence of events in hot carrier degradation follows a well-defined physical chain. Understanding each step helps in identifying which device parameters are affected and why.

• High lateral electric field near drain (E = VDS/L for short channels) accelerates channel electrons beyond thermal equilibrium energy.
• Impact ionization near pinch-off region generates electron-hole pairs, producing measurable substrate current Isub — a direct reliability monitor.
• Hot electrons with energy greater than 3.2 eV overcome the Si-SiO2 barrier and inject into the gate oxide, becoming trapped.
• Trapped oxide charge and newly created interface traps shift Vth upward and degrade carrier mobility (reduced gm).
• LDD (Lightly Doped Drain) structure is the primary process-level mitigation, spreading the peak field and reducing Isub significantly.
• Reducing VDD is the most effective system-level mitigation; each 100 mV reduction in VDS can increase device lifetime by an order of magnitude due to the exponential dependence.
• Modern FinFETs show reduced HCI due to better electrostatic channel control, but the effect is not eliminated at advanced nodes.

Quick Revision

• Hot carriers are electrons (nMOS) or holes (pMOS) accelerated to energies much higher than kT by the high lateral electric field near the drain.
• Impact ionization generates substrate current: Isub = A · IDS · exp(−B / (VDS − VDsat)). Isub is maximum near VGS = VDS/2 + Vth.
• Hot electron injection into gate oxide creates interface traps and oxide trapped charge, causing Vth to increase and gm to decrease over time.
• LDD (Lightly Doped Drain) is the primary process fix. Reducing VDD is the most effective operational fix.
• Device lifetime under HCI: τ ∝ (Isub/IDS)^(−n), where n ≈ 2–4. Lower Isub/IDS means longer lifetime.
• GATE trap: HCI is worst for nMOS (electron mobility higher, so higher Isub). pMOS is less susceptible but not immune.
• HCI is a time-dependent degradation mechanism — distinct from oxide breakdown (TDDB), which is also field-driven but affects different failure modes.