Leakage Power Reduction

As CMOS transistors scale below 100 nm, leakage power has grown from a negligible background term to a significant fraction of total chip power. Unlike dynamic power, leakage flows even when the chip is idle with no switching activity. Controlling leakage is therefore essential for standby power management in mobile SoCs and is a key GATE topic under low-power VLSI design.

Core Concept Explanation

Leakage power is static power that flows through transistors even when they are supposed to be off. The dominant contributor in modern CMOS is sub-threshold leakage, which arises because a MOSFET does not switch off abruptly at V_GS = V_T. Below threshold, the drain current decreases exponentially but does not become zero. With billions of transistors on a chip, even nanoampere leakage per transistor adds up to significant total standby power.

Gate oxide tunneling leakage emerged as a serious concern when SiO2 gate oxide thickness fell below 2 nm in sub-65 nm nodes. At such thicknesses, electrons tunnel quantum-mechanically through the oxide even without a channel forming. The solution was to replace SiO2 with high-k dielectric materials such as HfO2 (hafnium dioxide). A high-k dielectric allows a physically thicker oxide layer while maintaining the same or better gate capacitance, thereby suppressing tunneling current without sacrificing drive strength.

Junction leakage flows through the reverse-biased source-body and drain-body p-n junctions. While normally small, it increases with temperature and with increased junction area. In very short channel devices, Drain-Induced Barrier Lowering (DIBL) further aggravates sub-threshold leakage by allowing the drain electric field to lower the source potential barrier, effectively reducing V_T at high V_DS and increasing off-state current.

Mathematical Expression

Sub-threshold leakage current follows an exponential relationship with the gate-to-source voltage and threshold voltage. The expression is I_sub = I_0 · exp((V_GS - V_T) / n·V_T) where I_0 is a process-dependent current, n is the sub-threshold slope factor (typically 1.3 to 1.5), and V_T = kT/q is the thermal voltage (approximately 26 mV at room temperature).

Increasing the threshold voltage V_T exponentially reduces sub-threshold leakage. This is the basis of multi-threshold voltage (multi-Vt) design. In a typical standard cell library, three flavors exist: low-Vt (LVT) for speed-critical paths with higher leakage, standard-Vt (SVT) for balanced use, and high-Vt (HVT) for non-critical paths with lowest leakage. By assigning HVT cells to slack-rich paths, total chip leakage is significantly reduced with minimal timing impact.

Practical Understanding

High-k metal gate (HKMG) technology, introduced around the 45 nm node by Intel, replaced SiO2 with HfO2 and simultaneously replaced the poly-silicon gate with a metal gate. The metal gate eliminates poly depletion effects and further improves gate control. This combination became standard for all advanced nodes and is the primary reason gate oxide leakage is no longer the dominant leakage mechanism in modern FinFETs.

Body biasing is another leakage reduction technique. In reverse body biasing (RBB), the well voltage is adjusted to increase V_T during standby mode, exponentially suppressing sub-threshold leakage. Forward body biasing (FBB) reduces V_T during active mode to recover speed. Adaptive body biasing systems combine both modes dynamically and are used in low-power microprocessors.

Power gating, which completely disconnects the supply voltage from idle circuit blocks, effectively reduces leakage to near zero in the gated domain during standby. It is the most aggressive leakage reduction technique and is covered in detail in the Power Gating article.

Given:
A cell has I_0 = 100 nA, n = 1.4, V_T (thermal) = 26 mV
Threshold voltage V_T = 0.4 V, V_GS = 0 V (transistor off)

Why this formula applies:
Off-state transistor still carries sub-threshold current exponentially

Formula:
I_sub = I_0 × exp((V_GS - V_T) / (n × V_th))

Substitution:
I_sub = 100×10⁻⁹ × exp((0 - 0.4) / (1.4 × 0.026))

Calculation:
Exponent = -0.4 / 0.0364 = -10.99
exp(-10.99) ≈ 1.67 × 10⁻⁵
I_sub = 100×10⁻⁹ × 1.67×10⁻⁵

Final Answer: I_sub ≈ 1.67 pA per transistor

Note: Increase V_T by 100 mV (to 0.5 V):
Exponent = -0.5/0.0364 = -13.74
I_sub reduces by factor exp(-2.75) ≈ 0.064  (93.6% reduction!)

Exam Tip: Sub-threshold leakage is exponentially sensitive to V_T. A 100 mV increase in threshold voltage reduces leakage by approximately 10x at room temperature. GATE problems frequently test this exponential relationship.

Mechanism of High-k and Multi-Vt

• Sub-threshold leakage is the dominant leakage component in sub-100 nm CMOS. It flows between drain and source even when V_GS is below V_T due to weak inversion channel.
• High-k dielectrics such as HfO2 allow physically thicker gate insulation at the same equivalent oxide thickness (EOT), eliminating quantum tunneling through the gate.
• Multi-Vt design assigns HVT cells to non-critical paths and LVT cells only to critical (timing-limited) paths. This optimizes leakage without violating timing constraints.
• Reverse body biasing increases V_T during standby, exponentially reducing I_sub. This technique is effective in bulk CMOS where the well contact is accessible.
• Power gating offers the largest leakage reduction by cutting the supply voltage rail entirely, but requires careful management of wake-up latency and state retention.

Quick Revision

• Leakage power sources: sub-threshold (dominant), gate oxide tunneling, junction reverse leakage, DIBL-enhanced leakage.
• I_sub = I_0 · exp((V_GS - V_T) / n·Vth). Exponential dependence on V_T means small V_T increase gives large leakage reduction.
• High-k dielectric (HfO2) replaces SiO2 to suppress gate tunneling while maintaining gate capacitance.
• Multi-Vt: HVT for non-critical paths (low leakage), LVT for critical paths (high speed). SVT is the balanced default.
• Body biasing: RBB in standby raises V_T; FBB in active mode lowers V_T for performance.
• Exam trap: Leakage does NOT decrease with lower frequency. Only dynamic power reduces with lower f. Leakage is frequency-independent.
• DIBL worsens leakage in short-channel devices by reducing effective V_T at high drain voltages.