Pass Transistor Logic

Standard complementary CMOS logic uses both pMOS and nMOS transistors in every gate, which consumes area and increases input capacitance. Pass Transistor Logic (PTL) is an alternative logic style that uses transistors as controlled switches in a signal path, rather than as pull-up or pull-down current sources. PTL can implement complex functions with far fewer transistors, making it attractive for compact cells like multiplexers, XOR gates, and transmission gates. However, it introduces critical circuit challenges, most notably threshold voltage drop and signal degradation, that must be understood for both design and examination purposes.

Core Concept Explanation

In standard CMOS gates, the transistors drive the output by actively sourcing or sinking current between VDD and GND. In pass transistor logic, transistors are connected directly in the signal path — the input signal is passed through the transistor channel to the output, rather than being regenerated from the supply rails. The transistor behaves as a voltage-controlled switch: when the control gate voltage turns the transistor ON, the signal passes; when the gate turns it OFF, the signal path is broken and the output floats (high-impedance).

The fundamental PTL element is a single nMOS transistor with its source connected to the input signal, drain connected to the output, and gate connected to a control signal. This can implement functions like AND (if input is VDD, output = control gated by input), multiplexing (two pass transistors with complementary controls select between two inputs), and XOR (using a network of pass transistors with complementary and non-complementary inputs). A 2-to-1 multiplexer, for instance, requires only 2 pass transistors in PTL versus 8–10 transistors in full CMOS logic.

The primary circuit challenge in PTL is the threshold voltage drop problem. When a logic HIGH (VDD) is passed through an nMOS transistor with its gate also at VDD, the transistor turns ON and begins to charge the output node. As the output voltage rises, the source-to-gate voltage (VGS) of the nMOS transistor equals VDD - Vout. The transistor remains ON only as long as VGS > VTn. When Vout reaches VDD - VTn, the transistor turns OFF and the output is left at VDD - VTn, not VDD. This is a degraded logic high level.

Similarly, a pMOS pass transistor with gate at GND passes logic LOW correctly (output reaches GND), but when passing logic HIGH (VDD), it correctly reaches VDD. However, pMOS suffers a corresponding problem with logic LOW: the output gets stuck at |VTp| above GND instead of reaching GND. This complementary behavior — nMOS passes 0 well but degrades 1, pMOS passes 1 well but degrades 0 — directly motivates the Transmission Gate (TG) design.

Transmission Gate and Signal Restoration

A Transmission Gate consists of an nMOS and a pMOS transistor connected in parallel between the input and output, with complementary control signals on their gates (if nMOS gate = Ctrl, then pMOS gate = NOT_Ctrl). When Ctrl = 1 (nMOS ON) and NOT_Ctrl = 0 (pMOS ON), both transistors conduct simultaneously. The nMOS handles the low-to-high transition up to VDD-VTn, and then the pMOS (which is still ON because its VSG = VDD - Vout > |VTp|) continues charging the output all the way to VDD. Similarly for pulling output to GND, the pMOS handles VTp above GND and the nMOS completes the discharge to 0. The result is a full-swing bidirectional switch with no threshold voltage penalty.

Even with transmission gates, PTL circuits are not self-restoring. Each pass transistor stage introduces a small voltage drop or slope degradation, and in a cascade of multiple PTL stages, the signal level degrades cumulatively. For this reason, static CMOS inverter buffers are inserted periodically in PTL chains — typically every 2–4 stages — to restore full-swing logic levels. The tradeoff is between the area savings from PTL and the overhead of restoration inverters.

Practical Understanding

PTL is used selectively in modern standard cell libraries. Cells that benefit most are those implementing XOR/XNOR, multiplexers, and certain adder structures. For example, a 1-bit full adder implemented in PTL requires approximately 16 transistors versus 28 in standard CMOS, a significant area reduction. The CPL (Complementary Pass-transistor Logic) style always uses differential inputs and outputs to eliminate the need for NMOS-only pass of HIGH signals, at the cost of doubled wiring and area for complementary signal pairs.

A key consideration is noise margin degradation. The degraded high level (VDD - VTn) means that the next gate receiving this signal sees a logic high that is weaker than VDD. If the next gate is an nMOS-input stage, it may still switch correctly, but the noise margin is reduced by VTn. In deep submicron processes with low VDD (0.9–1.2V) and relatively large VTn (0.3–0.4V), this can leave barely 0.5–0.8V of logic high level, making noise margin inadequate and motivating the use of transmission gates or level restoring circuits.

The body effect also worsens threshold voltage degradation in cascaded pass transistors. In a series of nMOS pass transistors, the intermediate node voltages are above GND, causing the source-body voltage VSB of each transistor to be nonzero. This increases VTn beyond its zero-bias value, worsening the threshold drop. For a cascade of n nMOS pass transistors, the output logic high is approximately VDD - n×VTn (simplified), which rapidly degrades for even modest cascade depths.

Given:
VDD = 1.8 V, VTn = 0.45 V, VTp = -0.40 V
Body effect coefficient γ = 0.4 V^0.5, 2|φF| = 0.8 V
Cascade of 2 nMOS pass transistors (both gates at VDD = 1.8 V)

Why this formula applies:
Each nMOS pass transistor charges the next node until VGS = VTn.
For the first stage: Vout1 = VDD - VTn0 (zero-bias threshold)
For the second stage: VSB is nonzero → VTn increases due to body effect.

Formula:
VTn(VSB) = VTn0 + γ × (sqrt(VSB + 2|φF|) - sqrt(2|φF|))

Stage 1 output:
Vout1 = VDD - VTn0 = 1.8 - 0.45 = 1.35 V

Body effect at stage 2:
VSB = Vout1 = 1.35 V (source of stage 2 nMOS is at 1.35 V, body at GND)
VTn(VSB) = 0.45 + 0.4 × (sqrt(1.35 + 0.8) - sqrt(0.8))
          = 0.45 + 0.4 × (sqrt(2.15) - sqrt(0.8))
          = 0.45 + 0.4 × (1.467 - 0.894)
          = 0.45 + 0.4 × 0.573
          = 0.45 + 0.229 = 0.679 V

Stage 2 output:
Vout2 = VDD - VTn(VSB) = 1.8 - 0.679 = 1.121 V

Final Answer:
After 2 nMOS pass transistors: output high level = 1.121 V (vs. ideal 1.8 V)
Degradation = 0.679 V — over 37% of VDD lost.
This clearly demonstrates why transmission gates or level restorers are needed in PTL designs.

Exam Tip: For GATE, the nMOS pass transistor output high is VDD - VTn when gate = VDD. If body effect is included in a cascaded problem, VTn increases for each stage due to rising source voltage, worsening degradation. Transmission gates solve this — both pass fully with complementary controls. Remember: nMOS passes strong 0, weak 1; pMOS passes strong 1, weak 0.

Quick Revision

• Pass transistor logic: transistors act as switches in the signal path, not as current drivers. Output is taken directly from the transistor channel.
• nMOS pass transistor: passes logic 0 (GND) fully but limits logic 1 to VDD - VTn. This is the threshold voltage drop problem.
• pMOS pass transistor: passes logic 1 (VDD) fully but limits logic 0 to |VTp| above GND.
• Transmission gate = nMOS in parallel with pMOS (complementary controls). Passes both logic levels fully with no threshold penalty.
• Body effect worsens cascaded PTL: rising source voltage increases VTn, causing further degradation per stage. Vout_high = VDD - VTn(VSB) with VSB growing at each stage.
• Signal restoration: static CMOS inverter buffers must be inserted every 2–4 PTL stages to restore full-swing logic levels.
• GATE trap: The threshold drop is only for the direction where the transistor type is weak (nMOS weak for 1, pMOS weak for 0). For logic 0 through nMOS, the output correctly reaches GND with no degradation.