Power Gating

When an entire circuit block is idle for an extended period, even multi-Vt cell assignment leaves residual leakage flowing through every transistor. Power gating addresses this by inserting a high-Vt sleep transistor in series with the supply or ground rail, effectively disconnecting the block from VDD when it is not needed. This technique achieves the deepest leakage reduction possible in active chips and is fundamental to modern mobile SoC design.

Core Concept Explanation

A sleep transistor is a high-Vt MOSFET placed between the actual power supply (VDD or GND) and the virtual supply rail (VVDD or VGND) of a logic block. When the sleep signal is asserted, the transistor turns off and the logic block is electrically isolated. Since no current path exists from drain to source through an off transistor, leakage within the block effectively drops to the sleep transistor's own leakage, which is very low because it uses a high-Vt device.

The technique is implemented using MTCMOS (Multi-Threshold CMOS) cells. In MTCMOS, the standard logic cells use low-Vt or standard-Vt transistors for performance, while the footer (NMOS) or header (PMOS) sleep transistors use high-Vt devices to minimize their own leakage when off. The combination achieves both performance during active operation and near-zero leakage during sleep.

Power gating requires careful design of the power domain. All signals crossing the boundary between a gated domain and an always-on domain must pass through isolation cells that clamp outputs to a known logic level when the domain is powered off. Without isolation, a floating output from the powered-off domain can cause shoot-through current in always-on logic receiving that signal.

Mathematical Expression

The sleep transistor must be sized to supply the peak current of the entire logic block without causing excessive voltage drop on the virtual supply rail. The IR drop constraint is ΔV = I_peak × R_sleep where R_sleep is the on-resistance of the sleep transistor and ΔV must remain below approximately 100 mV to avoid timing violations within the logic block. For large blocks, multiple sleep transistors are distributed across the block in parallel to reduce the effective resistance.

The leakage saving is quantified as the ratio of block leakage in active mode to residual leakage in sleep mode. For a block with N standard cells, active leakage is P_leak_active = N × I_cell_leak × V_DD. In sleep mode, nearly all of this is eliminated; only the sleep transistor's own high-Vt leakage remains, typically two to three orders of magnitude lower than the collective cell leakage.

Practical Understanding

State retention is a major design challenge in power gating. When power is removed, all flip-flop state is lost. If the state must be preserved across sleep periods, state retention flip-flops are used. These cells include a shadow latch powered by a separate always-on supply that saves state just before power is removed and restores it upon wake-up.

Wake-up latency is the time required from asserting the wake signal to the block being fully functional. During wake-up, the virtual supply rail must charge to a valid voltage, which involves an inrush current through the sleep transistor. The wake-up sequence must be controlled carefully using a power sequencer to avoid large simultaneous inrush currents across multiple blocks that could cause supply noise.

In modern SoC design, entire power islands such as the GPU, modem, or memory controller are individually power-gated. Each island has its own power switch, isolation cells, and retention strategy. Fine-grained power gating at block level and coarse-grained at IP level together give the power management unit a wide range of control.

Given:
Logic block peak current I_peak = 20 mA
Allowable IR drop ΔV = 80 mV
Number of parallel sleep transistors to find: N
Each sleep transistor R_on = 5 Ω

Why this formula applies:
Sleep transistor IR drop must stay below ΔV to avoid timing issues

Formula:
ΔV = I_peak × (R_on / N)
N = I_peak × R_on / ΔV

Substitution:
N = 0.020 × 5 / 0.080

Calculation:
N = 0.1 / 0.08

Final Answer: N = 1.25 → Use 2 sleep transistors in parallel

Verification: ΔV = 0.020 × (5/2) = 0.020 × 2.5 = 50 mV < 80 mV ✓

Exam Tip: GATE may ask what happens if isolation cells are missing in a power-gated design. Answer: floating outputs from the OFF domain can drive logic in the ON domain to an unknown state, causing shoot-through current and functional failures.

Mechanism of Sleep Transistor Operation

• The sleep transistor must be sized for the peak current demand of the gated block. Undersizing causes excessive IR drop on the virtual supply, violating timing within the block.
• MTCMOS uses high-Vt sleep transistors to minimize their own leakage in sleep mode, while standard or low-Vt cells in the logic block provide the needed performance.
• Isolation cells are mandatory at all output signals crossing from the OFF domain to an always-on domain. They prevent floating logic values from causing shoot-through current.
• State retention flip-flops use a shadow latch connected to the always-on supply to save and restore state across power-off periods, enabling seamless wake-up.
• Level shifters are needed when signals cross between power domains operating at different supply voltages, which is common in multi-voltage SoC designs.

Quick Revision

• Power gating inserts HVt sleep transistors in series with VDD or GND rail of idle blocks, reducing leakage by 100x to 1000x.
• MTCMOS = low/std-Vt logic cells + high-Vt sleep transistor. Performance maintained during active; leakage minimized in sleep.
• Sleep transistor sizing: ΔV = I_peak × R_on. Multiple transistors in parallel lower R_on to meet IR drop budget.
• Isolation cells clamp output signals from gated domain to prevent X-propagation into always-on logic.
• Retention flip-flops save state in always-on shadow latch; restore on wake-up.
• Exam trap: Power gating eliminates leakage but does NOT save dynamic power. Clock gating reduces dynamic power, not leakage.
• Wake-up latency is a key design cost of power gating. Blocks that wake up frequently may spend more energy on wake-up transitions than they save from leakage reduction.