ROM/PROM Design

Read-Only Memory (ROM) stores fixed data that persists without power, making it essential for boot code, lookup tables, and microcode storage in digital systems. Unlike RAM, ROM data is determined at fabrication or programming time and cannot be modified during normal operation. Understanding NOR-based and NAND-based ROM structures is important for VLSI design because the two architectures offer fundamentally different tradeoffs in area, speed, and output drive capability.

Core Concept Explanation

A ROM is fundamentally a combinational circuit that maps a binary address to a binary data word. Internally, the address drives a row decoder that asserts exactly one wordline at a time. Each wordline selects a row of cells. The cells in that row either connect their bitline to GND (representing a logic 0 in NOR-type, or logic 1 in NAND-type depending on polarity convention) or leave it floating. The output is then read through sense amplifiers or output buffers.

In a NOR-based ROM, each memory cell is an NMOS transistor connected between the bitline and GND, with its gate connected to the wordline. When the wordline is high, any transistor present in that row pulls its bitline to GND. If no transistor exists at an intersection, the bitline remains at VDD through a pull-up device. The bitline output is thus the NOR function of all wordlines connected to it.

In a NAND-based ROM, cells are connected in series along each bitline. All transistors in the selected row must conduct for current to flow. If one transistor is absent (a logic 0 is stored), the series chain is broken and the bitline stays high. NAND ROM offers much smaller cell area because series-connected transistors share diffusion regions, but has higher access time because the series resistance is larger.

A PROM (Programmable ROM) is a ROM that comes with all bits set to 1 (or 0) at fabrication and is programmed exactly once by the user. This is done by selectively blowing fuses or anti-fuses using high current pulses. After programming, the PROM behaves identically to a mask ROM. PROM is used when small production volumes make custom mask ROMs uneconomical.

Mathematical Expression

For a ROM with n address lines, the number of rows is 2^n. If the output word width is m bits, the total number of cells in the array is 2^n x m. The decoder is an n-to-2^n binary decoder consuming approximately 2^n logic gates in a standard implementation, though tree decoders reduce gate count by accepting increased propagation delay.

Access time for NOR ROM is approximately: T_access = T_decoder + T_bitline_discharge, where T_bitline_discharge = C_BL x V_swing / I_cell. For NAND ROM, if k transistors are in series, the effective resistance seen by the bitline capacitor is k x R_on per transistor, making T_bitline slower by a factor of k compared to a single NOR cell. This is why NOR is preferred for fast random-access applications while NAND suits denser storage.

Practical Understanding

NOR ROM is widely used in embedded microcontrollers for storing boot firmware because of its fast random-access property. Any address can be read with roughly uniform access time, which suits instruction fetch where each opcode fetch is independent. NAND ROM, however, is compact and suited for bulk storage where sequential reads are dominant.

The programming density of NOR vs NAND ROM is dramatically different. In NAND, a single bitline column contains series-stacked cells sharing source and drain diffusions, so each cell area can approach 4F squared (where F is the minimum feature size). NOR cells each need their own source contact, pushing cell size to 10F squared or more. This is the fundamental reason why NAND dominates in flash memory storage while NOR flash is used for code storage.

Given:
ROM array with n = 8 address lines, m = 16-bit output word
NOR cell pull-down current I_cell = 50 uA
Bitline capacitance C_BL = 120 fF
Voltage swing V_swing = 1.0 V

Why this formula applies:
Bitline discharges from VDD through a single NMOS cell in NOR ROM.
T_discharge = C_BL x V_swing / I_cell

Formula:
Array size = 2^n x m cells
T_discharge = C_BL * V_swing / I_cell

Substitution:
Array size = 2^8 x 16 = 256 x 16 = 4096 cells
T_discharge = (120e-15 * 1.0) / 50e-6

Calculation:
T_discharge = 120e-15 / 50e-6 = 2.4e-9 s

Final Answer:
Array size = 4096 cells (4 Kbits)
Bitline discharge time = 2.4 ns

Exam Tip: GATE frequently asks to compare NOR and NAND ROM on area and speed. Remember: NOR is faster (parallel discharge) but larger area. NAND is slower (series discharge) but smaller area. For the same capacity, NAND ROM always has smaller die area.

• NOR ROM: each cell is a single NMOS from bitline to GND. Present transistor pulls bitline low when its wordline fires. Cells are in parallel, so any one can pull down independently. Output is active-low.
• NAND ROM: cells are in series on the bitline. The full series chain must conduct for the bitline to go low. One absent transistor (open circuit) prevents current flow, keeping bitline high. Compact but slow.
• PROM uses fuse or anti-fuse elements. Fuse-based PROM ships with all 1s and fuses are blown to program 0s. Anti-fuse PROM ships with all 0s and anti-fuses are broken down to program 1s.
• NOR access time is O(1) in terms of series transistors. NAND access time grows linearly with the number of series cells per column, making it unsuitable for fast random-access uses.
• Column decoder and output sense amplifiers are shared between NOR and NAND ROM architectures. The only difference is the cell structure within the array.

Quick Revision

• NOR ROM: cells in parallel, fast access, large cell area (about 10F squared), suited for code storage.
• NAND ROM: cells in series, slow access, small cell area (about 4F squared), suited for data storage.
• Array size = 2^n rows x m columns for n address bits and m-bit output word.
• PROM = field-programmable once using fuse or anti-fuse. Mask ROM = factory programmed, lowest cost at high volume.
• Access time for NOR: T = C_BL x V / I_cell. For NAND with k series transistors: T increases by factor k.
• GATE trap: NOR ROM output is active-low (transistor present means bitline pulled low = sense as logic 0 unless inverted). Clarify polarity convention in the question before answering.