Lambda Rules

In VLSI physical design, translating a circuit schematic into a manufacturable layout requires an intermediate representation that captures topology without worrying about exact dimensions. Stick diagrams serve precisely this purpose. They use color-coded lines to represent diffusion, polysilicon, and metal layers, allowing a designer to plan connectivity and layer interactions quickly. Lambda rules provide the scaling framework that makes these diagrams technology-independent.

Core Concept: Lambda Rules and Stick Diagrams

A lambda rule defines every geometric dimension in a layout as an integer multiple of λ, where λ is half the minimum printable feature size of a given process node. For example, at a 180 nm node, λ = 90 nm. This abstraction, introduced by Mead and Conway, allows the same design to be ported to a different technology simply by changing the value of λ without redrawing each layer separately.

Stick diagrams sit one level above the full layout but one level below the schematic. They are drawn using lines and dots on a grid, where each line represents a conducting layer and each dot or crosshatch represents a contact or via. The diagram shows which layers cross, which layers connect, and where transistors are formed (wherever a polysilicon line crosses a diffusion region). No actual dimensions are drawn at this stage.

The fundamental value of stick diagrams is planning. A designer can verify that the intended connectivity is achievable, identify potential design-rule violations before committing to full layout, and estimate routing complexity. In competitive exams, stick diagrams frequently appear as questions where you are asked to identify which layers are crossing and whether a valid transistor is formed.

Mathematical Expression: Lambda-Based Minimum Rules

The Mead-Conway lambda rules specify minimum dimensions and spacings for each layer. These are universally standardized and appear directly in GATE-level questions. The key rules for a generic CMOS process are as follows. Polysilicon minimum width is 2λ and minimum spacing between two poly lines is 3λ. Metal-1 minimum width is 3λ with a spacing of 3λ. A contact cut is 2λ by 2λ, and it must be surrounded by at least 1λ of metal on each side. The transistor channel length (drawn) equals the poly width, which is 2λ at minimum.

These rules translate directly into a hierarchy. The design rule ensures that lithographic and etch tolerances do not cause two features to merge or open-circuit. If λ scales from 100 nm to 65 nm, every rule automatically scales with it. The designer does not need to relearn any spacing numbers; only λ changes.

Practical Understanding: Constructing a Stick Diagram

To construct a stick diagram for a CMOS gate, begin by drawing horizontal rails for VDD and GND. Then draw vertical diffusion strips for PMOS (connected to VDD) and NMOS (connected to GND). Polysilicon lines run vertically and cross both diffusion strips to form the gates of the respective transistors. The input signal connects to the poly. The output node connects horizontally in Metal-1 between the drains of the PMOS and NMOS transistors. Contact cuts are shown as solid dots wherever a layer transitions from poly or diffusion to metal.

A practical concern is the placement of contacts. A contact cannot be placed right at the boundary of a diffusion region because the enclosure rule requires the contact to be at least 1λ inside the active area boundary. Violating this causes a DRC error in the actual layout. Recognizing this in a stick diagram helps a designer reroute before wasting time in full layout.

Numerical Example

Given:
Process node: 250 nm CMOS, so λ = 125 nm
Minimum poly width rule: 2λ
Minimum poly-to-poly spacing: 3λ
Contact size: 2λ × 2λ
Metal-1 minimum width: 3λ

Why this formula applies:
All lambda rules scale linearly with λ, so absolute dimensions are derived by multiplication.

Formula:
Absolute dimension = Rule_multiplier × λ

Substitution:
Min poly width = 2 × 125 nm = 250 nm
Min poly spacing = 3 × 125 nm = 375 nm
Contact size = 2 × 125 nm = 250 nm (each side)
Metal-1 width = 3 × 125 nm = 375 nm

Calculation:
Total pitch for two adjacent poly lines = poly width + spacing
= 250 nm + 375 nm = 625 nm

Final Answer:
Minimum poly pitch at 250 nm node = 625 nm (= 5λ)
This means two gate lines cannot be placed closer than 625 nm center-to-center.

Exam Tip: In GATE and university exams, if λ is given, immediately convert all rules to absolute nm before solving. A common trap is applying the multiplier to the feature size directly instead of to λ. Remember: feature size = 2λ, so λ = feature size / 2.

Mechanism: How Stick Diagrams Map to Full Layout

• Wherever a polysilicon line crosses a diffusion region, a transistor is automatically formed. This is the most fundamental rule in stick diagrams.
• Two lines from the same layer that intersect form a short circuit. Two lines from different layers that cross do not connect unless a contact or via symbol is explicitly shown.
• Contacts (poly-to-metal or diffusion-to-metal) and vias (metal-to-metal) are represented as solid filled dots at the junction point.
• VDD and GND rails are drawn in Metal-1 as horizontal lines at the top and bottom of the cell. All transistor connections must reach these rails through contacts.
• Lambda rules enforce minimum widths and spacings: 2λ for poly width, 3λ for poly spacing, and 2λ x 2λ for contacts. These constraints drive the minimum cell height and width during floor planning.

Quick Revision

• λ = half the minimum feature size. All layout rules are expressed as multiples of λ for technology independence.
• Stick diagram uses colored lines: green for N-diffusion, orange for P-diffusion, purple for polysilicon, blue for Metal-1. Dots indicate contacts and vias.
• Poly crossing diffusion = transistor formed. No explicit symbol needed. This is the core reading rule for stick diagrams.
• Formula recall: Minimum poly width = 2λ, poly spacing = 3λ, contact = 2λ × 2λ, Metal-1 width = 3λ.
• Exam trap: λ = feature size / 2, not feature size itself. Always halve the node dimension to get λ before applying any rule multiplier.
• Stick diagrams do not encode actual dimensions. They only show topology and layer interactions. Dimensions are added later using λ rules during full layout.
• Same-layer crossing without a contact implies a short. Different-layer crossing without a via implies no connection.