Transmission Gate Logic

In standard CMOS logic, the pull-up network uses PMOS transistors and the pull-down network uses NMOS transistors. This complementary structure is effective but doubles the transistor count for complex functions. Transmission gate (TG) logic offers an alternative approach that uses the unique bidirectional conduction property of CMOS transmission gates to implement functions like XOR and multiplexers with significantly fewer transistors, which is especially valuable in high-density VLSI layouts.

Core Concept: What is a Transmission Gate

A transmission gate consists of an NMOS transistor and a PMOS transistor connected in parallel, with their drain and source terminals connected to the same input and output nodes. The NMOS gate is driven by a control signal C, and the PMOS gate is driven by the complement C'. When C is high, both transistors turn on simultaneously, allowing the signal at the input to pass to the output. When C is low, both transistors turn off, disconnecting input from output.

The reason for using both NMOS and PMOS in parallel is related to the threshold voltage problem in pass transistor logic. A standalone NMOS transistor cannot pass a logic high level cleanly because its output voltage is limited to V_DD - V_th, where V_th is the NMOS threshold voltage. Similarly, a standalone PMOS cannot pass a logic low cleanly. By using both in parallel, the NMOS handles the low side (near 0V) and the PMOS handles the high side (near VDD), ensuring both logic levels pass without voltage degradation.

TG-Based XOR Gate

The XOR gate is one of the most important functions in digital arithmetic, and TG logic implements it far more efficiently than standard CMOS. In the TG-based XOR, input A acts as the control signal for two transmission gates. The first TG (controlled by A=0) passes signal B directly when A is low. The second TG (controlled by A=1) passes the complement of B (from an inverter) when A is high. The outputs of both TGs are connected together to form the XOR output.

When A=0: TG1 is on (C=0 for PMOS side, meaning PMOS gate of TG1 is connected to A'=1, and NMOS gate is A=0 — this is an important detail to trace carefully in the actual circuit). The logic result is that when A=0, B passes through, giving output=B=A XOR B. When A=1, B' passes through, giving output=B'=A XOR B since A XOR 1=A'. The entire XOR requires only 4 transistors for the TG gates plus 2 transistors for the inverter generating B', totaling 6 transistors, compared to 12 transistors in standard CMOS implementation.

TG-Based Multiplexer

A 2-to-1 multiplexer (MUX) is implemented with just two transmission gates. TG1 is controlled by select signal S and passes input A when S=1. TG2 is controlled by S' and passes input B when S=0. The outputs of both TGs are tied together to form the MUX output. This requires only 4 transistors total (2 per TG), compared to 12 transistors in a conventional CMOS MUX using standard gate logic.

However, TG-based MUX output has high impedance when driving large capacitive loads, because the TG is a pass element and not an actively driven gate. In practice, a buffer (two inverters) is added at the output to restore drive strength. Even with the buffer, the total transistor count (4 + 4 = 8) is still significantly less than the 12 needed in standard CMOS implementation, making TG-based design very area-efficient for critical logic blocks.

Mathematical Expression

The TG can be modeled as a voltage-controlled switch with an ON resistance. When the TG is conducting, it acts as a resistor with a channel resistance approximately equal to the parallel combination of the NMOS and PMOS on-resistances: R_TG = (R_n * R_p) / (R_n + R_p). A chain of N TGs in series has a total resistance of N * R_TG. The propagation delay through a TG-chain driving a load capacitance C_L is given by t_p = 0.69 * N * R_TG * C_L. This delay grows linearly with the number of series TGs, so long TG chains must be broken with buffers.

Practical Understanding

TG logic is extensively used in implementing full adders with fewer transistors, D flip-flops using TG-based latches, and barrel shifters using pass transistor arrays. The transmission gate D latch, which uses 2 TGs and 2 inverters (8 transistors total), is a standard building block in CMOS sequential circuits and is more compact than a conventional CMOS latch. TG-based logic does consume slightly more power in certain switching conditions due to short-circuit currents during the transition period when both the TG and its load inverter are simultaneously conducting, but this is manageable in well-designed layouts.

Solved Numerical Example

A TG-based 2:1 MUX has R_NMOS = 5 kOhm, R_PMOS = 8 kOhm (on-resistance), and drives a load capacitance of 50 fF. Calculate the propagation delay through one TG and compare it with a 3-TG series chain driving the same load.

Given:
R_n = 5 kΩ, R_p = 8 kΩ, C_L = 50 fF = 50 × 10⁻¹⁵ F

Why this formula applies:
TG acts as a switch with parallel resistance.
Delay through RC network: t_p = 0.69 × R_TG × C_L

Formula:
R_TG = (R_n × R_p) / (R_n + R_p)  [parallel combination]
t_p = 0.69 × R_TG × C_L

Substitution:
R_TG = (5000 × 8000) / (5000 + 8000)
     = 40,000,000 / 13,000
     = 3076.9 Ω ≈ 3.08 kΩ

Single TG delay:
t_p1 = 0.69 × 3076.9 × 50 × 10⁻¹⁵
     = 0.69 × 1.538 × 10⁻¹⁰
     = 1.06 × 10⁻¹⁰ s ≈ 106 ps

Three-TG series chain delay:
t_p3 = 0.69 × 3 × R_TG × C_L
     = 3 × 106 ps = 318 ps

Final Answer:
Single TG delay ≈ 106 ps
3-TG chain delay ≈ 318 ps (3× increase)
Conclusion: Long TG chains must be broken with inverter buffers to limit delay.

Exam Tip: Transmission gate logic is a highly favored topic in GATE and VLSI design exams. Key points to remember: (1) TG requires complementary control signals C and C'. (2) NMOS passes 0 strongly, PMOS passes 1 strongly — together they pass both levels cleanly. (3) TG-based 2:1 MUX needs only 4 transistors. (4) TG-based XOR needs 6 transistors (4 for TGs plus 2-transistor inverter for B'). (5) Long TG chains cause delay proportional to N and need buffering.

Mechanism: TG XOR and MUX Signal Paths

• A transmission gate requires complementary control signals. The NMOS gate receives C and the PMOS gate receives C'. Both transistors turn on together when C=1, and both turn off when C=0.
• In a TG-based XOR, input A controls which version of B reaches the output. When A=0, B passes directly. When A=1, B' (inverted B) passes, naturally implementing the XOR function with only 6 transistors.
• A TG-based 2:1 MUX requires only 4 transistors (two TGs) versus 12 transistors in a conventional CMOS MUX. The select signal S controls which input is connected to the output.
• The TG D latch uses two TGs and two inverters (8 transistors total). When CLK=1, the first TG passes D to the output. When CLK=0, the second TG closes the feedback loop through an inverter, holding the state.
• TG logic delay is modeled as RC delay: t_p = 0.69 * R_TG * C_L for a single TG. For a chain of N series TGs, delay = 0.69 * N * R_TG * C_L, so chains longer than 3-4 TGs should be broken with buffers.

Quick Revision

• Transmission gate = NMOS parallel with PMOS, driven by C and C' respectively. Acts as a bidirectional switch with full voltage swing.
• NMOS alone: passes 0 well, passes 1 degraded (V_DD - V_thn). PMOS alone: passes 1 well, passes 0 degraded. TG together: both logic levels pass cleanly.
• TG-based XOR: 6 transistors (4 for two TGs + 2-transistor inverter for B'). A controls which TG is active, selecting B or B'.
• TG-based 2:1 MUX: 4 transistors only. S controls TG1 (passes A) and S' controls TG2 (passes B).
• TG delay formula: t_p = 0.69 × R_TG × C_L, where R_TG = R_n || R_p (parallel combination of on-resistances).
• Exam trap: TG logic saves transistors but introduces resistive delay and requires buffering for long chains. Do not assume TG output is always full-swing driven without a buffer.
• D latch using TG requires 8 transistors. It is the standard compact latch in CMOS flip-flop designs.