Side-by-side comparison
| Parameter | Mealy | Moore State Machine |
|---|---|---|
| Output Depends On | Current state AND current input | Current state only |
| Output Timing | Combinational — can glitch with input | Registered — changes only on clock edge |
| Number of States | Fewer states for same behaviour | More states (one state per output combination) |
| State Diagram | Output labelled on transition arcs | Output labelled inside state circles |
| Response Speed | Faster — responds in same clock cycle | Slower — one clock cycle latency |
| Glitch Risk | Higher — output can glitch on input noise | Lower — output stable between clock edges |
| Hardware Complexity | Slightly simpler — fewer flip-flops | Slightly more complex — extra states |
| Implementation in HDL | Two always blocks (state, output) | Three always blocks or Moore-explicit coding |
| GATE/Exam Frequency | High — minimum state questions | High — output timing and Moore diagram |
| Real Example | Serial bit pattern detector (overlapping) | Traffic light controller |
Key differences
The key distinction: Mealy outputs fire immediately when inputs change, even between clock edges, so a noisy input line can generate spurious outputs — a real problem in 3.3 V FPGA I/O without input synchronisers. Moore outputs change only at the clock edge, adding one cycle of latency but eliminating glitches. For the same sequence detector, a Mealy machine typically needs n states where Moore needs n+1. In Verilog, a Moore machine uses three always blocks; Mealy can be done in two.
When to use Mealy
Use a Mealy machine when response speed within the same clock cycle is critical, such as a serial 1-of-N pattern detector on a fast data link where overlapping sequences must be detected without losing a cycle.
When to use Moore State Machine
Use a Moore machine when output stability is paramount, such as a traffic light controller where the light must hold its colour for a full clock period without any combinational glitches affecting pedestrian signals.
Recommendation
For GATE and university exams, choose the Moore machine when the question asks for glitch-free outputs. Choose Mealy when minimising state count — the question usually specifies which to use, but when it does not, state your assumption explicitly.
Exam tip: GATE regularly tests minimum state reduction for sequence detectors — draw the Mealy diagram first, minimise states using implication chart, then convert to Moore by splitting states if required.
Interview tip: Interviewers at VLSI and FPGA companies expect you to code both machines in Verilog; be ready to write the two-always-block Mealy template from memory and explain why Moore avoids output glitches.